Analog Devices Inc. DC552A
- Part No.:
- DC552A
- Manufacturer:
- Analog Devices Inc.
- Package:
- Datasheet:
-
DC552A.pdf
- Description:
- LTC1420CGN - 12-BIT 10MSPS ADC (
- Quantity:
- Payment:

- Shipping:

Inventory:1,142
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DC552A from Analog Devices (formerly Linear Technology) is a demonstration circuit board for the LTC1420CGN 12-bit, 10MSPS analog-to-digital converter. It provides a validated PCB layout with configurable reference (VREF = 2.048V or 4.096V), programmable PGA gain (1× or 2×), dual/single-supply operation, and buffered digital outputs - used for rapid evaluation of high-speed ADC performance in precision data acquisition systems.
For engineers reviewing the DC552A datasheet, DC552A pinout, DC552A application, or DC552A equivalent, key selection considerations include its support for 10MSPS sampling, ±2.5V or ±5V input ranges via jumper-configurable SENSE and GAIN pins, 2's complement/binary output coding, and compatibility with 3V–5V digital output supplies (OVDD/VCC).
Technical Context
DC552A implements the LTC1420CGN in a fully assembled, test-ready configuration with discrete RC input filtering (R18/C6), 50Ω clock termination (R17), and a 74ACT16373 transparent latch for output buffering. The board supports both single-supply (+5V VDD, GND) and dual-supply (+5V VDD, −5V VSS) analog operation, with VCM fixed at +2.5V for single-supply mode.
Reference voltage selection (2.048V or 4.096V) is achieved via JP1–JP3 SENSE jumpers; PGA gain (1× or 2×) is set by JP4; differential or single-ended analog input is configured via JP5; and output coding format (2's complement or straight binary) is selected via JP6 - all without soldering or component changes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core IC | LTC1420CGN - 12-bit, 10MSPS successive-approximation ADC in 28-pin SOIC package |
| Analog Supply | Single: +5V VDD/GND; Dual: +5V VDD/−5V VSS - enables rail-to-rail input with VCM = +2.5V |
| VREF Options | 2.048V (JP3) or 4.096V (JP1) - sets full-scale input range per PGA gain setting |
| PGA Gain | 1× (JP4 right) or 2× (JP4 left) - scales input range to ±VREF/2 or ±VREF/4 respectively |
| Digital Output Drive | 74ACT16373 latch with OVDD/VCC = 3V–5V - provides noise-immune, edge-aligned parallel data output |
| Input Interface | +AIN/−AIN BNC connectors with JP5 selectable −AIN = GND (dual supply) or VCM (single supply) |
| Clock Input | CLK BNC connector with 50Ω ground-terminated R17 - accepts low-jitter encode clocks <5ns edge rates |
Availability
DC552A is available at Aetrix Electronics and suitable for precision data acquisition, high-speed sensor interfacing, and mixed-signal prototyping requiring stable component supply and validated reference design implementation.
Supply support for DC552A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies.
The DC552A belongs to Analog Devices' demonstration circuit (DC) series, designed to accelerate evaluation and system integration of precision ADCs like the LTC1420CGN in test, measurement, and instrumentation applications.
FAQ
What is the primary function of the DC552A demonstration circuit?
The DC552A demonstration circuit is a fully assembled evaluation platform for the LTC1420CGN 12-bit, 10MSPS ADC. It enables immediate functional validation, AC performance testing, and layout reference extraction. The DC552A includes all necessary support circuitry - input filtering, clock termination, reference configuration, PGA gain selection, and digital output latching - allowing engineers to assess the DC552A in real-world signal chain conditions without custom PCB development.
Does the DC552A support both single-supply and dual-supply analog operation?
Yes, the DC552A supports both configurations. For single-supply operation, connect VDD = +5V and VSS = GND, with JP5 set to the right two pins to tie −AIN to VCM (+2.5V). For dual-supply operation, connect VDD = +5V and VSS = −5V, and set JP5 to the left two pins to tie −AIN to GND. The DC552A's analog section is fully configurable for either mode using on-board jumpers without hardware modification.
How is the reference voltage (VREF) configured on the DC552A?
VREF on the DC552A is set via three SENSE pin jumpers (JP1–JP3). JP1 connects SENSE to GND for VREF = 4.096V; JP3 connects SENSE to VREF for VREF = 2.048V; JP2 leaves SENSE open for external VREF drive (≈1kΩ input impedance). These options directly determine the full-scale input range of the LTC1420CGN within the DC552A, and are user-selectable without soldering.
What digital output interface does the DC552A provide?
The DC552A provides parallel CMOS-compatible digital outputs via a 40-pin header, delivering all 12 data bits, an overflow flag (OVF), and a buffered clock (CLKOUT) for synchronous latching. Output coding (2's complement or straight binary) is selected via JP6. The 74ACT16373 latch ensures clean, edge-aligned data valid timing - critical for reliable capture by FPGA or microcontroller interfaces when using the DC552A.
Can the DC552A be used with a 3.3V digital supply?
Yes, the DC552A supports OVDD and VCC supplies from +3V to +5V, making it compatible with 3.3V logic families. Both the LTC1420CGN's digital output drivers and the 74ACT16373 latch operate correctly across this range. When using 3.3V, ensure the host system's input thresholds align with ACT-series logic levels, and maintain short, impedance-controlled traces from the DC552A's 40-pin output header to preserve signal integrity during high-speed data capture.
DC552A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Packaging:
- Box
- Product Status:
- Active
- Number of A/D Converters:
- 1
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 10M
- Data Interface:
- Parallel
- Input Range:
- ±2.048V
- Power (Typ) @ Conditions:
- 250mW @ 10MSPS
- Utilized IC / Part:
- LTC1420
- Contents:
- Board(s)
DC552A FAQ
1.How can I place an order for DC552A through Aetrix?
Please submit a Request for Quotation (RFQ) for DC552A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DC552A reliable?
The price and inventory of DC552A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DC552A is usually 5 days.
3.What payment methods are accepted for DC552A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DC552A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DC552A?
DC552A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DC552A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DC552A?
For technical support, including DC552A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DC552A requirements.
6.How does Aetrix verify that DC552A is sourced from the original manufacturer or authorized distributors?
All DC552A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DC552A meets industry standards.
7.What is the process for return or replacement of DC552A?
All DC552A units undergo pre-shipment inspection (PSI). If there is an issue with DC552A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DC552A part is unused and in its original packaging.
Return procedure for DC552A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DC552A Tags

-
1083
Adafruit Industries LLC

-
1085
Adafruit Industries LLC

-
ADS7038Q1EVM-PDK
Texas Instruments

-
ADS8688EVM-PDK
Texas Instruments

-
EVAL-AD7606C18FMCZ
Analog Devices Inc.

-
ADS1232REF
Texas Instruments

-
EVAL-AD4134FMCZ
Analog Devices Inc.

-
EVAL-AD7768FMCZ
Analog Devices Inc.

-
ADC128S102EVM
Texas Instruments

-
ADS124S08EVM
Texas Instruments

-
ADC6140EVM-PDK
Texas Instruments

-
ADS7066EVM-PDK
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

