Texas Instruments DDC101U

Overview

DDC101U from Burr-Brown is a 20-bit monolithic charge-digitizing analog-to-digital converter optimized for low-level current inputs (e.g., photosensors), featuring adaptive delta modulation, correlated double sampling (CDS), 0.9ppm rms noise at low signal levels, ±5V dual-supply operation, and serial digital output with programmable oversampling up to 256×. It performs integrated current-to-voltage conversion, integration, gain amplification, A/D conversion, and digital filtering in a single IC for precision instrumentation applications.

For engineers reviewing the DDC101U datasheet, DDC101U pinout, DDC101U application, or DDC101U equivalent, this page delivers verified technical context, validated pin functions, confirmed dynamic range behavior (500pC unipolar full-scale), real-world CDS error correction performance, and precise supply/temperature specifications - all directly traceable to the official Burr-Brown DDC101 datasheet (SBAS029, PDS-1211E).

Technical Context

The DDC101U implements a patented adaptive delta modulation architecture with internal capacitor DAC (CDAC) and autozeroed comparator, enabling virtual-ground charge integration at user-defined TINT (64µs–106µs). Its tracking logic updates the CDAC at 2MHz to maintain input node stability while accumulating charge on CINT.

Digital filtering applies programmable oversampling (L = 1–256) and correlated double sampling (CDS) to eliminate offset, charge injection, and reset noise by subtracting two oversampled data points - one at integration start, one at end - yielding 18-bit no-missing-codes unipolar resolution and 16-bit bipolar resolution.

Key Specifications

Pinout & Package

DDC101U is housed in a 24-lead SOIC package (θJA = 100°C/W), with separate analog/digital power and ground domains, dedicated reference buffer bypass, and dual-clock architecture (SYSTEM CLOCK and DATA CLOCK) for noise isolation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar charge-digitizing ADC applications.

Compared with ADS1256IDBT and LTC2418CGN#PBF, the DDC101U uniquely integrates charge accumulation, adaptive delta modulation, and correlated double sampling in a single monolithic IC - delivering verified 0.9ppm rms noise at low signal levels and eliminating external integration components required by alternatives.

Availability

DDC101U is available at Aetrix Electronics and suitable for infrared pyrometry, CT scanner data acquisition systems, and precision chemical analyzer designs requiring stable component supply, long-term lifecycle continuity, and traceable sourcing for industrial OEM programs.

Supply support for DDC101U includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Burr-Brown Corporation was a U.S.-based analog semiconductor pioneer, acquired by Texas Instruments in 2000, renowned for high-precision data converters, amplifiers, and interface ICs targeting demanding measurement applications.

The DDC101U belongs to Burr-Brown's monolithic charge-digitizing ADC product line, designed specifically for direct interfacing with low-current sensors in scientific instrumentation, medical imaging, and industrial process control where low-level linearity and noise rejection are critical.

FAQ

What is the maximum input current the DDC101U can accurately digitize?

The DDC101U supports a maximum average input current of ±7.8µA for unipolar operation. At this level, the minimum integration time is 64µs. For longer integration periods (e.g., 1ms), the full-scale current drops to 500nA to maintain 500pC total charge. Exceeding ±7.8µA risks tracking errors unless external capacitance is used to buffer transient pulses - confirmed in Section 5 of the DDC101U datasheet (SBAS029).

Does the DDC101U require an external voltage reference?

Yes, the DDC101U requires an external –2.5V reference connected to pin 23 (VREF). This reference sets the full-scale range and enables precise multi-channel synchronization. The internal reference buffer (pin 24) must be bypassed with a 10µF capacitor to ensure CDAC stability - specified in Section 3 Pin Descriptions and Figure 24 of the DDC101U datasheet.

How does Correlated Double Sampling (CDS) improve measurement accuracy in the DDC101U?

CDS in the DDC101U eliminates integration-cycle-dependent errors - including input offset voltage, charge injection, and reset noise - by capturing and subtracting two oversampled data points: one at the start and one at the end of integration. This technique reduces noise to 0.9ppm rms at low signal levels, as measured with CSENSOR = 0pF and L = 8 - detailed in Section 2 Specifications and Figure 3 of the DDC101U datasheet.

Can multiple DDC101U devices be synchronized for simultaneous sampling?

Yes, multiple DDC101U units can be synchronized using a shared SYSTEM CLOCK and FDS (Final Data Point Start) signal. The FDS input (pin 8) initiates the final oversampling interval, and the end of that interval triggers the next integration - enabling deterministic, aligned sampling across channels. Daisy-chaining via DATA INPUT/OUTPUT further simplifies interconnects - described in Section 4 Timing Diagrams and Figure 4 of the DDC101U datasheet.

What is the purpose of the TEST In pin (pin 22) on the DDC101U?

The TEST In pin activates an internal 100nA ±20nA DC current source that injects directly into the analog input node (pin 3). This provides a factory-traceable diagnostic stimulus for functional verification and system-level calibration - without requiring external test equipment. Activation increases quiescent current by ~1mA, as documented in Section 3 Pin Descriptions of the DDC101U datasheet.