Texas Instruments DDC112UG4

Overview

DDC112UG4 from Texas Instruments is a dual-channel, 20-bit monolithic charge-digitizing analog-to-digital converter optimized for low-current photodetector interfaces. It features continuous dual-switched integrator architecture, programmable full-scale ranges (up to 1000 pC with external capacitors), ±0.025% integral linearity (max), and 3.2 ppm rms noise at Range 5 (250 pC). It operates from single +5 V supplies and supports cascaded serial output for multi-channel data acquisition in medical CT scanners and precision spectroscopy systems.

For engineers reviewing the DDC112UG4 datasheet, DDC112UG4 pinout, DDC112UG4 application, or DDC112UG4 equivalent, this page delivers verified technical context, validated pin functions, confirmed package mapping (SO-28), real-world application constraints (e.g., VREF stability requirements, CSENSOR-dependent noise), and two rigorously cross-checked alternative parts with documented functional trade-offs.

Technical Context

The DDC112UG4 implements a true integrating architecture with two independent input channels, each containing two switched integrators (A/B) that operate interleaved: while one side integrates, the other is digitized by a shared delta-sigma modulator and digital filter. Integration time (TINT) is programmable from 50 µs to 1 ms, directly setting system bandwidth and noise floor - e.g., 500 µs yields 3.2 ppm rms noise at 250 pC full-scale.

Full-scale range selection uses three RANGE pins (RANGE0–RANGE2) to configure internal integration capacitors (12.5–87.5 pF) or enable external capacitor mode (RANGE=000); all four integrators (CH1A/CH1B/CH2A/CH2B) share the same range setting unless external caps differ per channel. The device requires a stable +4.096 V reference (VREF) for both capacitor reset and ∆Σ conversion, with VREF current scaling inversely with TINT (e.g., 150 µA at 500 µs).

Key Specifications

Pinout & Package

DDC112UG4 is housed in a 28-pin Small Outline (SO-28) package with gull-wing leads and 0.050-inch pitch. Pin functions are electrically validated per TI SBAS085B Rev. October 2004. All analog and digital grounds are physically separated to minimize coupling; VREF and CAPx pins require local high-frequency decoupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar charge-digitizing ADC applications.

Compared with DDC112UG4, AD7739BRUZ offers higher resolution but lacks native current-input capability and real-time interleaving, while LTC2418CGN#PBF provides superior DC specs but no integrated charge-measurement path - making DDC112UG4 uniquely suited for photodiode and ionization chamber interfaces requiring simultaneous dual-channel, low-noise, programmable integration.

Availability

DDC112UG4 is available at Aetrix Electronics and suitable for CT scanner data acquisition systems, infrared pyrometers, liquid/gas chromatography detectors, and clinical blood analysis instruments requiring stable component supply with long-term manufacturability assurance.

Supply support for DDC112UG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with over 50 years of innovation in precision data converters and sensor interface solutions.

The DDC112UG4 belongs to TI's precision analog-to-digital converter product line, designed specifically for direct digitization of low-current sensors in medical imaging, analytical instrumentation, and industrial process control where charge integration, noise immunity, and multi-channel synchronization are critical.

FAQ

What is the maximum full-scale input charge supported by the DDC112UG4?

The DDC112UG4 supports up to 1000 pC full-scale input charge when configured in external capacitor mode (RANGE2–RANGE0 = 000) with user-selected integration capacitors. With internal capacitors only, the maximum is 350 pC (Range 7). This capability allows direct interfacing with high-output photodiodes or ionization chambers without external gain stages, preserving signal integrity in the DDC112UG4 signal chain.

How does the DDC112UG4 achieve low-noise performance with photodiode inputs?

The DDC112UG4 achieves 3.2 ppm rms noise at 250 pC full-scale through its true integrating architecture, which inherently rejects high-frequency noise, combined with a digital filter stage and careful layout isolation of analog/digital grounds. Its input bias current (0.1–10 pA) minimizes dark current errors, and VREF stability requirements (<0.1 Vpp ripple) ensure integration accuracy - all validated in the DDC112UG4 electrical characteristics table.

Can multiple DDC112UG4 devices be synchronized for simultaneous sampling?

Yes - the DDC112UG4 supports synchronized operation via shared CLK and CONV signals. When multiple units use the same system clock and CONV timing, their integration cycles align, enabling coherent sampling across channels. The cascaded serial interface (DIN/DOUT) further simplifies firmware readout, allowing >100 DDC112UG4 devices to share a single microcontroller SPI bus without additional GPIO overhead.

What is the role of the TEST pin on the DDC112UG4, and how is it used?

The TEST pin on the DDC112UG4 enables on-chip self-calibration by injecting a known ~13 pC charge packet into both input integrators during conversion. When asserted before a CONV edge, it grounds IN1/IN2 and applies test charge - allowing verification of gain, linearity, and channel matching without external stimulus. This function is fully documented in the DDC112UG4 timing diagrams and electrical characteristics tables.

Why does the DDC112UG4 require separate AGND and DGND connections?

The DDC112UG4 separates AGND and DGND to prevent digital switching noise from modulating the ultra-precise analog integration process. Internal circuitry routes analog return currents (integrators, VREF, AVDD) to AGND and digital return currents (DCLK, DOUT, DVDD) to DGND. Connecting them at a single point near the device - not at the power supply - maintains >100 dB PSRR and prevents 0.5 ppm FSR errors caused by ground bounce in the DDC112UG4 measurement path.