Texas Instruments DDC112Y/2K
- Part No.:
- DDC112Y/2K
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-TQFP
- Datasheet:
-
DDC112Y/2K.pdf
- Description:
- IC ADC 20BIT SIGMA-DELTA 32TQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,326
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DDC112Y/2K from Texas Instruments is a dual-channel, 20-bit monolithic charge-measuring analog-to-digital converter optimized for low-current photodetector and sensor digitization. It features continuous dual-switched integrator architecture, programmable full-scale ranges (up to 1000 pC with external capacitors), ±0.025% integral linearity error (max), and 3.2 ppm rms noise at Range 5 (250 pC). Designed for CT scanner data acquisition systems and precision process control instrumentation.
For engineers reviewing the DDC112Y/2K datasheet, DDC112Y/2K pinout, DDC112Y/2K application, or DDC112Y/2K equivalent, key selection considerations include its TQFP-32 package, –40°C to +85°C industrial temperature grade, cascaded serial interface support, and dual-integrator timing independence from data retrieval clocking.
Technical Context
The DDC112Y/2K implements two independent input channels, each with paired switched integrators (A/B) enabling continuous current integration: while one integrator digitizes, the other integrates. Its delta-sigma modulator and digital filter deliver 20-bit resolution with 3.2 ppm rms noise at 500 µs integration time and 10 MHz system clock.
Full-scale range is selected via RANGE0–RANGE2 pins controlling internal capacitor banks (12.5–87.5 pF) or bypassed for external capacitor use (e.g., up to 1000 pC). The device operates from single +5 V supplies (AVDD/DVDD), uses VREF = +4.096 V for integrator reset and ADC reference, and supports daisy-chained serial output via DCLK/DXMIT/DOUT/DIN.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 20-bit output with no missing codes; delivers 1 ppm effective resolution over full scale. |
| Integral Linearity Error | ±0.025% reading ±1.0 ppm FSR (max); ensures high-accuracy quantization across dynamic range. |
| Input Noise | 3.2 ppm of FSR rms (Range 5, CSENSOR = 0 pF); enables sub-picoampere current measurement fidelity. |
| Conversion Rate | 2–3 kHz in continuous mode; supports real-time sampling for medical and analytical instrumentation. |
| Supply Voltage | AVDD/DVDD = 4.75–5.25 V; single-supply operation simplifies power design in isolated sensor front ends. |
| Reference Voltage | VREF = +4.096 V nominal; defines full-scale charge range and sets integrator reset level and ADC reference. |
| Operating Temperature | –40°C to +85°C; qualified for industrial and medical equipment deployed in demanding environments. |
Pinout & Package
TQFP-32 package with 0.5 mm pitch; thermally enhanced for stable operation at up to +85°C ambient. Pin 1 is CAP1A (top-left corner, marked dot); exposed thermal pad (pin 33) must be soldered to PCB ground plane for thermal management.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Dual analog current inputs | Accept low-level photodiode/sensor currents; internally referenced to AGND; support direct connection without transimpedance amplifiers. |
| CAP1A/CAP1B, CAP2A/CAP2B | External integration capacitor terminals | Enable user-defined full-scale range up to 1000 pC; pairs per channel must match capacitance for channel balance. |
| RANGE0–RANGE2 | 3-bit full-scale range select | Selects internal capacitor bank (8 ranges, 12.5–87.5 pF); RANGE=000 enables external capacitor mode. |
| CONV | Integrator side control | High = Integrator A active; Low = Integrator B active; must be synchronized to CLK rising edge ±10 ns. |
| DCLK, DXMIT, DOUT, DIN, DVALID | Synchronous serial interface | Supports daisy-chaining >100 units; DVALID asserts low when 20-bit result is ready in shift register. |
| VREF | External reference input | +4.096 V reference used for integrator reset and ADC conversion; requires low-noise buffered source. |
| AGND, DGND, AVDD, DVDD | Analog/digital supply and ground | Separate analog/digital domains minimize noise coupling; AGND–DGND offset limited to ±0.3 V. |
Key Features
| Feature | Design Value |
|---|---|
| Dual continuous-switched integrators per channel | Enables uninterrupted current integration - one side integrates while the other digitizes, eliminating dead time. |
| Programmable full-scale range (8 internal + external) | Internal ranges span –1.4 to +350 pC; external mode supports up to 1000 pC, adapting to diverse sensor sensitivities. |
| Cascadable serial interface | DIN/DOUT chaining reduces interconnect count and PCB routing complexity in multi-channel DAS systems. |
| Low input bias current (0.1–10 pA typ) | Preserves signal integrity from ultra-low-current sources like photodiodes and pyroelectric sensors. |
| Digital filtering with 3.2 ppm rms noise | Reduces quantization and thermal noise without external post-processing, improving effective resolution. |
Applications
| CT Scanner DAS | Infrared Pyrometer |
|---|---|
Use Scenario: Digitizing current outputs from scintillation detector arrays in computed tomography systems. IC Role / Device Role / Timing Role: Dual-channel charge digitizer performing simultaneous integration and conversion on X-ray pulse trains. Use Value: 20-bit resolution and <3.5 ppm noise enable accurate attenuation coefficient mapping across high-dynamic-range scans. |
Use Scenario: Converting thermopile or pyroelectric sensor current into calibrated temperature readings. IC Role / Device Role / Timing Role: Precision integrating ADC rejecting EMI and 50/60 Hz interference via programmable integration time. Use Value: ±0.025% linearity and low drift (<±3 ppm/°C offset) ensure traceable non-contact temperature accuracy over industrial operating range. |
| Liquid Chromatography Detector | Blood Analysis Instrumentation |
Use Scenario: Measuring low-level photocurrent from UV/Vis absorbance detectors in HPLC systems. IC Role / Device Role / Timing Role: High-resolution charge accumulator capturing transient peak signals with minimal baseline drift. Use Value: 3.2 ppm rms noise and 20-bit output resolve sub-nanogram analyte concentrations in chromatographic elution profiles. |
Use Scenario: Digitizing current from electrochemical biosensors in clinical blood gas or immunoassay analyzers. IC Role / Device Role / Timing Role: Dual-input integrator supporting simultaneous measurement of reference and sample channels. Use Value: Matched integral linearity (±0.1% range error match) and low crosstalk (<–120 dB) ensure precise ratiometric analysis critical for diagnostic reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar charge-digitizing ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7739BRUZ | Single-channel, 24-bit ΣΔ ADC; no dual-integrator architecture; requires external transimpedance amplifier for current input. | Lower channel density; suited for high-resolution single-sensor systems where integration time flexibility outweighs parallelism. | Choose AD7739BRUZ when absolute 24-bit resolution is prioritized over dual-channel concurrency and direct current input capability. |
| ADS1258IPWR | 8-channel, 24-bit ΣΔ ADC; multiplexed single integrator; 10 kSPS max; no programmable full-scale charge range. | Higher channel count but lacks dedicated charge integration; requires external I/V conversion and gain staging. | Choose ADS1258IPWR for multi-sensor voltage-output systems needing throughput >2 kSPS, not for direct low-current photodiode digitization. |
Compared with AD7739BRUZ and ADS1258IPWR, the DDC112Y/2K uniquely delivers true dual-channel concurrent charge integration with on-chip programmable full-scale ranges - eliminating external op-amps and enabling direct photodiode interfacing in space-constrained medical and analytical modules.
Availability
DDC112Y/2K is available at Aetrix Electronics and suitable for CT scanner data acquisition systems, infrared pyrometers, liquid/gas chromatography detectors, and blood analysis instrumentation requiring stable component supply across extended industrial temperature ranges.
Supply support for DDC112Y/2K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision data converters and sensor interface solutions.
The DDC112Y/2K belongs to TI's high-precision charge-digitizing ADC product line, engineered specifically for direct digitization of low-current photodetectors and scientific sensors in medical imaging and analytical instrumentation.
FAQ
What is the maximum full-scale input charge supported by the DDC112Y/2K?
The DDC112Y/2K supports up to 1000 pC full-scale input charge when configured in external capacitor mode (RANGE2–RANGE0 = 000). With internal capacitors only, the maximum is 350 pC (Range 7). This extended range allows direct interfacing with high-capacitance photodiode arrays or long-cable sensor configurations without signal attenuation. The DDC112Y/2K achieves this via dedicated CAP1A/CAP1B and CAP2A/CAP2B pins routed to external precision capacitors.
Does the DDC112Y/2K require separate analog and digital power supplies?
Yes, the DDC112Y/2K requires two independent +5 V supplies: AVDD for the analog section (integrators, reference, modulator) and DVDD for the digital interface (serial logic, shift register). AVDD and DVDD must each be 4.75–5.25 V, and AGND–DGND voltage difference must not exceed ±0.3 V to prevent noise coupling. This separation ensures the DDC112Y/2K maintains its specified 3.2 ppm rms noise and ±0.025% linearity performance in mixed-signal systems.
How does the DDC112Y/2K achieve continuous integration with only one delta-sigma converter?
The DDC112Y/2K achieves continuous integration using a dual-switched integrator architecture per channel: each input has two independent integrators (A and B). While integrator A accumulates charge, integrator B is digitized by the shared delta-sigma converter - and vice versa. The CONV pin controls which integrator is active, and timing is synchronized to CLK. This interleaving eliminates dead time, enabling uninterrupted current measurement - a core capability of the DDC112Y/2K unmatched by standard multiplexed ADCs.
Can multiple DDC112Y/2K devices be synchronized for time-aligned sampling?
Yes, multiple DDC112Y/2K devices can be synchronized using a common CLK and CONV signal distributed across all units. Because integration timing is controlled externally via CONV and CLK edges, and digitization is deterministic relative to those edges, sampling alignment across devices is achievable. The DDC112Y/2K's daisy-chain serial interface (DIN→DOUT) further enables coordinated readout without additional timing lines - critical for multi-slice CT scanner DAS implementations.
What is the role of the TEST pin on the DDC112Y/2K, and how is it used in calibration?
The TEST pin on the DDC112Y/2K initiates an internal self-test mode that injects calibrated 13 pC charge packets into both input channels' integrators. When asserted before a CONV edge, it grounds IN1/IN2 and applies test charge synchronously - enabling verification of gain, linearity, and channel matching without external stimulus. This function is documented in the DDC112Y/2K datasheet (SBAS085B) and supports factory and field calibration of blood analysis and chromatography instruments where traceable charge injection is required.
DDC112Y/2K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-TQFP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 20
- Sampling Rate (Per Second):
- 3k
- Number of Inputs:
- 2
- Input Type:
- Single Ended
- Data Interface:
- SPI
- Configuration:
- DSI-ADC
- Ratio - S/H:ADC:
- 2:1
- Number of A/D Converters:
- 1
- Architecture:
- Sigma-Delta
- Reference Type:
- External
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 5V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-TQFP (7x7)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
DDC112Y/2K FAQ
1.How can I place an order for DDC112Y/2K through Aetrix?
Please submit a Request for Quotation (RFQ) for DDC112Y/2K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DDC112Y/2K reliable?
The price and inventory of DDC112Y/2K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DDC112Y/2K is usually 5 days.
3.What payment methods are accepted for DDC112Y/2K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DDC112Y/2K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DDC112Y/2K?
DDC112Y/2K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DDC112Y/2K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DDC112Y/2K?
For technical support, including DDC112Y/2K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DDC112Y/2K requirements.
6.How does Aetrix verify that DDC112Y/2K is sourced from the original manufacturer or authorized distributors?
All DDC112Y/2K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DDC112Y/2K meets industry standards.
7.What is the process for return or replacement of DDC112Y/2K?
All DDC112Y/2K units undergo pre-shipment inspection (PSI). If there is an issue with DDC112Y/2K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DDC112Y/2K part is unused and in its original packaging.
Return procedure for DDC112Y/2K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DDC112Y/2K Tags

-
ADC081C021CIMKX/NOPB
Texas Instruments

-
MCP3021A5T-E/OT
Microchip Technology

-
TLA2024IRUGR
Texas Instruments

-
MCP3221A5T-E/OT
Microchip Technology

-
MCP3221A5T-I/OT
Microchip Technology

-
MCP3221A4T-E/OT
Microchip Technology

-
MCP3221A6T-E/OT
Microchip Technology

-
MCP3221A0T-E/OT
Microchip Technology

-
MCP3221A1T-E/OT
Microchip Technology

-
ADC121S021CIMFX/NOPB
Texas Instruments

-
MCP3001-I/MS
Microchip Technology

-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

