Texas Instruments DDC2256AZZF

Overview

DDC2256AZZF from Texas Instruments is a 24-bit, 256-channel current-input analog-to-digital converter with dual switched integrators per channel, ±2.5-V/1.8-V analog and 1.8-V digital supplies, and LVDS/CMOS serial output. It directly digitizes photodiode or X-ray sensor currents with simultaneous sampling, 58.8 µs minimum integration time, and ±0.025% integral linearity - deployed in CT scanner data acquisition systems.

For engineers reviewing the DDC2256AZZF datasheet, DDC2256AZZF pinout, DDC2256AZZF application, or DDC2256AZZF equivalent, key selection considerations include 256-channel current-input architecture, on-chip reference buffer and bypass capacitors, 14 × 16 mm² NFBGA-323 package, simultaneous charge capture without loss, and support for fA–µA input current ranges.

Technical Context

The DDC2256AZZF implements 256 input channels grouped into 16 banks of 16 inputs each, each bank serviced by one dual switched integrator and shared 24-bit ADC. Integration time is digitally adjustable from 58.8 µs to 100 ms, enabling precise measurement across six decades of current magnitude.

It uses a sigma-delta (SD) ADC architecture with internal reference buffering and integrated bypass capacitance, operating from split ±2.5-V analog rails plus dedicated 1.8-V analog (AVDD_18) and digital (DVDD) supplies. Output is serialized via low-noise LVDS or CMOS interface to minimize crosstalk in high-density medical imaging systems.

Key Specifications

Pinout & Package

The DDC2256AZZF is housed in a 14 mm × 16 mm, 323-ball NFBGA (package code ZZF) with 0.8 mm pitch and 1.66 mm max height. Ball mapping includes dedicated analog/digital ground planes (AGND/DGND), separate analog supply rails (AVDD, AVEE, AVDD_18), and differential clock inputs (CLKP/CLKM).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar current-input ADC applications.

Compared with ADAS1000-4BCPZ and ADS131M08IPBSR, the DDC2256AZZF uniquely delivers 256-channel simultaneous current integration in a single chip-eliminating 255 external TIAs, inter-channel skew, and PCB routing complexity inherent in multi-device solutions.

Availability

DDC2256AZZF is available at Aetrix Electronics and suitable for CT scanner data acquisition, photodiode array readout, and X-ray detection systems requiring stable component supply, long-term lifecycle support, and traceable sourcing for Class II medical device manufacturing.

Supply support for DDC2256AZZF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, designing and manufacturing analog ICs, embedded processors, and high-performance data converters for industrial, automotive, and medical applications.

The DDC2256AZZF belongs to TI's high-channel-count precision data acquisition product line, engineered specifically for direct digitization of low-level sensor currents in medical imaging and scientific instrumentation systems.

FAQ

What is the operating temperature range specified for the DDC2256AZZF?

The DDC2256AZZF is specified for operation from 0°C to +70°C ambient temperature. This range aligns with commercial and industrial medical imaging subsystem requirements, including CT detector modules mounted near rotating gantries. Thermal performance is supported by the on-board temperature sensor, which provides real-time die temperature data for system-level drift compensation. The DDC2256AZZF maintains its ±0.025% integral linearity and 24-bit resolution across this full range without derating.

Does the DDC2256AZZF require external reference components?

No, the DDC2256AZZF integrates a reference buffer and on-package 100 nF bypass capacitors for all supply rails, eliminating the need for external reference ICs or discrete decoupling networks. The device accepts an optional external reference via VREF_IN but operates fully self-contained using its internal buffered reference. This reduces PCB area by up to 35% compared to discrete reference solutions and improves long-term stability by removing solder-joint and layout-induced reference noise paths in the DDC2256AZZF signal chain.

How does the DDC2256AZZF achieve simultaneous sampling across 256 channels?

The DDC2256AZZF achieves true simultaneous sampling using 256 dedicated switched integrator cells-one per input-with globally synchronized reset and integration timing controlled by the CONV and CLKP/CLKM signals. Each integrator captures charge independently and concurrently; no time-division multiplexing is used. The resulting voltages are then digitized by 16 shared 24-bit sigma-delta ADCs, with output serialization preserving channel alignment. This architecture ensures zero inter-channel skew in the DDC2256AZZF, critical for coherent image reconstruction in CT and X-ray systems.

What package type and ball count does the DDC2256AZZF use?

The DDC2256AZZF uses a 14 mm × 16 mm, 323-ball NFBGA package with 0.8 mm pitch and 1.66 mm maximum height (package code ZZF). All balls are arranged in a defined array supporting automated optical inspection and standard reflow profiles. The package includes dedicated AGND/DGND/QGND balls for ground separation, isolated AVDD/AVEE/AVDD_18 supply balls, and differential LVDS-compatible I/O balls for SDOUT/SCLK. This mechanical implementation is documented in TI's ZZF0323A package outline drawing.

Can the DDC2256AZZF interface directly with an FPGA without level-shifting?

Yes, the DDC2256AZZF supports direct FPGA interfacing via its 1.8-V CMOS or LVDS serial output interface (SDOUT, SCLK, SDIN), both compliant with industry-standard FPGA I/O banks. When configured for CMOS mode, the DDC2256AZZF drives 1.8-V logic levels compatible with Artix-7, Kintex-Ultrascale+, and Cyclone 10 GX I/O standards. No external level shifters are needed-provided the FPGA bank is powered at 1.8 V and terminated per TI-recommended guidelines in the DDC2256AZZF datasheet.