My Inquiry
My Account
Texas Instruments DDC232CGXGR
- Part No.:
- DDC232CGXGR
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 64-LFBGA
- Datasheet:
-
DDC232CGXGR.pdf
- Description:
- IC ADC 20BIT SIGMA-DELTA 64NFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,788
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DDC232CGXGR from Texas Instruments is a 20-bit, 32-channel, current-input analog-to-digital converter with dual-switched integrator front-end architecture. It directly digitizes low-level photodiode currents (down to fA range) using on-chip integration and delta-sigma conversion, operates from +5V AVDD and +2.7V–+3.6V DVDD, and delivers ±0.025% integral linearity and 5.3ppm FSR rms noise in CT scanner DAS applications.
For engineers reviewing the DDC232CGXGR datasheet, DDC232CGXGR pinout, DDC232CGXGR application, or DDC232CGXGR equivalent, key selection criteria include its 32-channel current-input architecture, adjustable full-scale range (12.5pC to 350pC), continuous integration mode, daisy-chainable serial interface, and BGA-64 package compatibility with high-density medical imaging sensor arrays.
Technical Context
The DDC232CGXGR implements 32 independent input channels, each with two switched integrators enabling true continuous integration: while one side integrates input current, the other side undergoes digitization by the onboard delta-sigma ADC. Integration time is programmable from 166.5ms to 1s, supporting current measurement across 7 full-scale ranges (12.5pC to 350pC).
Its serial interface uses dedicated configuration pins (DIN_CFG/CLK_CFG/RESET) for register programming and synchronous data transfer via DCLK/DOUT/DVALID, with support for multi-device daisy-chaining. The device requires external +4.096V VREF and employs internal trimmed capacitors for range matching and offset stability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 20-bit output word with 19-bit no-missing-codes guarantee; enables precise quantization of ultra-low photocurrents. |
| Integral Linearity | ±0.025% of reading ±1.0ppm of FSR typical; ensures accurate end-point fidelity in calibrated medical imaging systems. |
| Input Noise | 5.3ppm of FSR rms at Range 7 (350pC), CSENSOR = 50pF; supports sub-picoampere signal resolution in photodiode arrays. |
| Data Rate | 3.125 kSPS maximum for DDC232C variant; matches timing requirements of slow-scan CT detector readout. |
| Power per Channel | 7 mW typical at 3.125 kSPS; enables thermally constrained multi-DDC232 designs in compact DAS modules. |
| Full-Scale Range | Programmable across 7 settings (12.5pC to 350pC); allows dynamic optimization for varying photodiode responsivity and gain staging. |
| Operating Temperature | 0°C to +70°C ambient; validated for use in industrial-grade CT scanner electronics without forced cooling. |
Pinout & Package
The DDC232CGXGR is housed in a 64-pin BGA package (10mm × 10mm, 0.8mm pitch) with separate analog/digital ground planes (AGND/DGND), dual power domains (AVDD = +5V, DVDD = +2.7V to +3.6V), and dedicated quiet analog ground (QGND) for low-noise integrator operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1–IN32 | Analog Input | 32 single-ended current-input terminals accepting fA–mA photocurrents; each paired with dual integrators for continuous acquisition. |
| CONV | Digital Input | Edge-triggered control signal selecting integration side (A/B); must be synchronized within ±10ns of CLK rising edge for optimal noise performance. |
| DVALID | Digital Output | Active-low strobe indicating valid data in shift register; enables deterministic timing for FPGA-based data capture without polling overhead. |
| DIN_CFG / CLK_CFG / RESET | Digital Input | Three-wire interface for 12-bit configuration register write; supports runtime adjustment of range, format, Clk_4x, and test mode. |
| VREF | Analog Input | +4.096V external reference input; directly sets integrator reset voltage and full-scale range-requires buffered low-noise source per Figure 6. |
| AGND / DGND / QGND | Ground Terminal | Physically isolated ground pins prevent digital switching noise from corrupting sensitive analog integration paths. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-switched integrator per channel | Enables uninterrupted current integration-no dead time between samples-critical for high-duty-cycle photodiode monitoring. |
| In-package bypass capacitance | Integrated 0.1µF capacitors reduce PCB component count and layout sensitivity for AVDD/DVDD decoupling near analog/digital cores. |
| Daisy-chainable serial interface | Single DOUT→DIN cascade path simplifies interconnection of multiple DDC232 devices in large-area detector arrays with minimal routing layers. |
| Adjustable integration time (166.5ms–1s) | Allows trade-off between noise floor and frame rate: longer tINT lowers rms noise but reduces maximum scan speed. |
| Range error match ≤0.5% FSR | Ensures consistent full-scale response across all 32 channels-eliminates per-channel calibration in production CT DAS assemblies. |
Applications
| CT Scanner Detector Array | Photodiode Sensor Module |
|---|---|
Use Scenario: Digitizing output from 32-element scintillator-photodiode arrays in third-generation CT gantries. IC Role / Device Role / Timing Role: Primary current-input ADC performing continuous integration and 20-bit digitization of X-ray-induced photocurrents. Use Value: Eliminates external op-amp transimpedance stages and multiplexers, reducing component count and thermal drift in sealed detector modules. |
Use Scenario: High-precision light-intensity measurement in lab-grade spectrophotometers with multi-anode photodiodes. IC Role / Device Role / Timing Role: Direct current-to-digital conversion with programmable integration time for adaptive exposure control. Use Value: Achieves 5.3ppm FSR noise at 350pC full scale, enabling <10fA resolution without cryogenic cooling. |
| X-Ray Flat Panel Detector | Industrial Radiography System |
Use Scenario: Reading out amorphous silicon photodiode arrays in digital radiography panels requiring >16-bit linearity. IC Role / Device Role / Timing Role: 32-channel parallel digitizer synchronizing integration windows across pixel columns via shared CONV/CLK. Use Value: Maintains ±0.025% integral linearity across temperature (0°C–70°C), ensuring consistent grayscale fidelity in diagnostic images. |
Use Scenario: Monitoring radiation dose in real-time during non-destructive testing of weld integrity in pipeline inspection tools. IC Role / Device Role / Timing Role: Low-power current digitizer operating from battery-supplied +5V/+3.3V rails in portable enclosures. Use Value: Delivers 7mW/channel power consumption, extending field-deployable system runtime without active cooling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar current-input ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DDC232CKGXGR | Same 32-channel architecture but rated for 6.2kSPS max data rate and 10mW/channel power; uses Clk_4x=1 mode for finer integration time quantization. | Better suited for faster-scanning CT systems requiring higher throughput; not drop-in compatible due to different default Clk_4x and Version bit settings. | Select DDC232CKGXGR only when >3.125kSPS sampling is required and system clock can support 20MHz CLK input. |
| DDC316IRGZT | 16-channel, 20-bit current-input ADC with 100kSPS max rate and 28mW/channel; uses different integrator topology and lacks daisy-chain configuration interface. | Targets high-speed, lower-channel-count applications like laser interferometry; incompatible pinout and register map prevents direct replacement. | Consider DDC316IRGZT only for new designs prioritizing speed over channel density and willing to redesign PCB layout and firmware interface. |
Compared with DDC232CGXGR, the DDC232CKGXGR offers higher speed at increased power and stricter clocking requirements, while the DDC316IRGZT trades channel count for speed and lacks the seamless daisy-chain capability essential for scalable multi-sensor systems.
Availability
DDC232CGXGR is available at Aetrix Electronics and suitable for CT scanner detector arrays, photodiode sensor modules, and X-ray flat panel detectors requiring stable component supply, long-term lifecycle support, and traceable sourcing for Class II medical electronics.
Supply support for DDC232CGXGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in precision analog, embedded processing, and high-reliability ICs for industrial, medical, and automotive markets.
The DDC232CGXGR belongs to TI's Direct Digital Current Converter (DDC) product line, engineered specifically for high-accuracy, multi-channel current digitization in medical imaging and scientific instrumentation where low noise, channel matching, and integration flexibility are critical.
FAQ
What is the full-scale input current range supported by the DDC232CGXGR?
The DDC232CGXGR supports seven programmable full-scale ranges from 12.5pC to 350pC (e.g., 12.5pC, 50pC, 100pC, up to 350pC), set via the 3-bit Range[2:0] field in the configuration register. Each range corresponds to a specific on-chip integration capacitor value (3pF to 87.5pF), and all 32 channels share the same selected range simultaneously. This allows system-level gain optimization without per-channel trimming.
How does the dual-switched integrator architecture in the DDC232CGXGR enable continuous current measurement?
The DDC232CGXGR assigns two independent integrators (Side A and Side B) to each of its 32 inputs. While one side integrates incoming photocurrent, the other side is digitized by the onboard delta-sigma ADC-enabling zero dead time between integration cycles. The CONV pin toggles integration sides in sync with CLK, ensuring uninterrupted signal capture essential for high-duty-cycle CT detector operation.
What are the power supply requirements for the DDC232CGXGR?
The DDC232CGXGR requires two independent supplies: AVDD = +4.75V to +5.25V (typical +5V) for analog circuitry including integrators and reference buffers, and DVDD = +2.7V to +3.6V (typical +3.0V) for digital logic and serial interface. Total power dissipation is 224–288mW, yielding 7mW/channel average-validated across 0°C to +70°C ambient.
Can the DDC232CGXGR be used in daisy-chain configurations, and what signals are required?
Yes, the DDC232CGXGR supports daisy-chaining via its dedicated serial interface: DOUT of one device connects to DIN of the next, while CLK, DCLK, CONV, and RESET are shared across all devices in the chain. This eliminates per-device clock distribution skew and reduces FPGA I/O count-enabling scalable readout of 64+, 96+, or 128-channel detector arrays using a single data bus.
What is the role of the VREF pin on the DDC232CGXGR, and why must it be buffered?
The VREF pin accepts a +4.096V external reference that resets the integration capacitors before each cycle and serves as the scaling reference for delta-sigma conversion. Because VREF variations directly cause full-scale range drift and offset errors, TI mandates buffering with a low-noise op-amp (e.g., OPA350) and RC filtering-as shown in Figure 6-to suppress noise and maintain stability during high-current charge/discharge transients. Unbuffered VREF causes measurable linearity degradation.
DDC232CGXGR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-LFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Number of Bits:
- 20
- Sampling Rate (Per Second):
- 6k
- Number of Inputs:
- 32
- Input Type:
- Single Ended
- Data Interface:
- SPI
- Configuration:
- ADC
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- 16
- Architecture:
- Sigma-Delta
- Reference Type:
- External
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 2.7V ~ 5.25V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 64-NFBGA (8x8)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
DDC232CGXGR FAQ
1.How can I place an order for DDC232CGXGR through Aetrix?
Please submit a Request for Quotation (RFQ) for DDC232CGXGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DDC232CGXGR reliable?
The price and inventory of DDC232CGXGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DDC232CGXGR is usually 5 days.
3.What payment methods are accepted for DDC232CGXGR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DDC232CGXGR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DDC232CGXGR?
DDC232CGXGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DDC232CGXGR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DDC232CGXGR?
For technical support, including DDC232CGXGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DDC232CGXGR requirements.
6.How does Aetrix verify that DDC232CGXGR is sourced from the original manufacturer or authorized distributors?
All DDC232CGXGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DDC232CGXGR meets industry standards.
7.What is the process for return or replacement of DDC232CGXGR?
All DDC232CGXGR units undergo pre-shipment inspection (PSI). If there is an issue with DDC232CGXGR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DDC232CGXGR part is unused and in its original packaging.
Return procedure for DDC232CGXGR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DDC232CGXGR Tags
-
ADC081C021CIMKX/NOPB
Texas Instruments
-
MCP3021A5T-E/OT
Microchip Technology
-
TLA2024IRUGR
Texas Instruments
-
MCP3221A5T-E/OT
Microchip Technology
-
MCP3221A5T-I/OT
Microchip Technology
-
MCP3221A4T-E/OT
Microchip Technology
-
MCP3221A6T-E/OT
Microchip Technology
-
MCP3221A0T-E/OT
Microchip Technology
-
MCP3221A1T-E/OT
Microchip Technology
-
ADC121S021CIMFX/NOPB
Texas Instruments
-
MCP3001-I/MS
Microchip Technology
-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
