Texas Instruments DDC232CGXGT

Overview

DDC232CGXGT from Texas Instruments is a 20-bit, 32-channel, current-input analog-to-digital converter with dual-switched integrator front-end architecture. It directly digitizes low-level photodiode currents (down to fA range), supports adjustable full-scale ranges up to 350 pC, delivers ±0.025% integral linearity and 5.3 ppm FSR rms noise, and operates in CT scanner detector acquisition systems requiring high-precision, continuous integration.

For engineers reviewing the DDC232CGXGT datasheet, DDC232CGXGT pinout, DDC232CGXGT application, or DDC232CGXGT equivalent, this page provides verified technical context, validated pin functions, confirmed package mapping to BGA-64, real-world application constraints for medical imaging and X-ray detection, and two rigorously cross-checked alternative parts with documented functional and parametric differences.

Technical Context

The DDC232CGXGT implements 32 parallel dual-switched integrators-each with two independent integration paths (Side A and Side B)-enabling true continuous current integration: while one side integrates input current, the other side undergoes delta-sigma A/D conversion. Integration time is programmable from 166.5 ms to 1 s via configuration register bits Range[2:0] and Clk_4x.

Its serial interface supports daisy-chaining across multiple devices using shared CLK and DCLK, with DVALID signaling valid data output and CONV controlling integrator-side selection. The device uses separate AVDD (+5 V) and DVDD (+2.7 V to +3.6 V) supplies, with dedicated AGND and DGND planes and on-package bypass capacitors to minimize PCB layout complexity.

Key Specifications

Pinout & Package

The DDC232CGXGT is housed in a 64-pin BGA package (10 mm × 10 mm, 0.8 mm pitch) with exposed thermal pad. Pin assignments follow TI's standard DDC232 footprint and are validated per SBAS331D Rev. D.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar current-input ADC applications.

Compared with DDC232CK, the DDC232CGXGT trades speed for lower power and relaxed timing margins; compared with ADAS1000-3, it offers 6.4× more channels and configurable full-scale range but no integrated biopotential features-making it strictly superior for multi-sensor industrial and medical imaging digitization.

Availability

DDC232CGXGT is available at Aetrix Electronics and suitable for CT scanner detector acquisition systems, photodiode sensor arrays, and X-ray detection systems requiring stable component supply, long-term lifecycle support, and traceable sourcing for Class II medical device manufacturing.

Supply support for DDC232CGXGT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-reliability components for industrial, automotive, and medical applications.

The DDC232 product line was designed specifically for direct digitization of ultra-low-current sensor outputs in radiation detection and medical imaging-replacing multi-component transimpedance + ADC solutions with single-chip precision and integration.

FAQ

What is the full-scale input range supported by the DDC232CGXGT?

The DDC232CGXGT supports eight programmable full-scale ranges from 12.5 pC (Range 0) to 350 pC (Range 7), selected via the 3-bit Range[2:0] field in its 12-bit configuration register. Each range corresponds to a factory-trimmed on-chip integration capacitor value (3–87.5 pF), enabling precise matching across all 32 channels without external components. This range flexibility allows the DDC232CGXGT to handle photodiode currents from femtoamperes to milliamperes depending on integration time and sensor capacitance.

How does the dual-switched integrator architecture in the DDC232CGXGT improve measurement continuity?

The DDC232CGXGT uses two independent integrators per channel (Side A and Side B) to eliminate dead time between measurements. While one side integrates incoming current, the other side is simultaneously digitized by the internal delta-sigma converter. The CONV pin toggles integration sides synchronously with the system clock (CLK), ensuring uninterrupted current accumulation-critical for capturing continuous photon flux in CT and X-ray applications. This architecture achieves true continuous integration without sacrificing resolution or linearity.

What are the power supply requirements for reliable operation of the DDC232CGXGT?

The DDC232CGXGT requires two independent supplies: AVDD = +4.75 V to +5.25 V (typical +5 V) for analog circuitry including integrators and reference buffer, and DVDD = +2.7 V to +3.6 V (typical +3.0 V) for digital I/O and configuration logic. AGND and DGND must be separated on the PCB and joined at a single point near the device. Supply current is 41–60 mA (analog) and 3.7–8.0 mA (digital), totaling 224–288 mW. Decoupling uses integrated 0.1 µF capacitors plus external 10 µF bulk capacitance per supply rail.

Can the DDC232CGXGT be daisy-chained with other DDC232 devices, and what signals are required?

Yes, the DDC232CGXGT supports daisy-chaining via its dedicated serial interface: DIN connects to DOUT of the upstream device, while DCLK, CLK, CONV, and RESET are shared across all devices in the chain. DVALID remains device-specific. Configuration is handled separately using DIN_CFG/CLK_CFG pins. This topology reduces FPGA or microcontroller pin count significantly-for example, 8 DDC232CGXGT devices require only 5 shared control lines plus one DIN/DOUT pair instead of 128 individual data lines-enabling scalable multi-sensor systems without bus contention.

What is the role of the VREF pin on the DDC232CGXGT, and why must it be buffered?

The VREF pin on the DDC232CGXGT supplies the reference voltage (+4.096 V nominal) used to reset integration capacitors before each cycle and serve as the scaling reference for the delta-sigma converter. Because VREF directly sets full-scale range and contributes to offset drift, TI mandates external buffering using a low-noise op-amp (e.g., OPA350) with a low-pass filter-as shown in Figure 6 of SBAS331D-to suppress noise and prevent voltage droop during high-current reset pulses (up to 650 mA peak). Unbuffered or poorly regulated VREF causes gain errors exceeding ±0.1% and degrades integral linearity beyond specification.