Texas Instruments DDC232CKZXGR

Overview

DDC232CKZXGR from Texas Instruments is a 20-bit, 32-channel, current-input analog-to-digital converter with dual-switched integrator front-end architecture. It operates on +5V analog and +2.7V to +3.6V digital supplies, delivers 6.2 kSPS maximum data rate, achieves ±0.025% integral linearity and 5.3 ppm FSR rms noise, and is optimized for photodiode-based detection in medical CT scanner DAS systems.

For engineers reviewing the DDC232CKZXGR datasheet, DDC232CKZXGR pinout, DDC232CKZXGR application, or DDC232CKZXGR equivalent, key selection criteria include its 32-channel current-input capability, adjustable full-scale range (up to 350 pC), continuous integration mode, daisy-chainable serial interface, and BGA-64 package compatibility with high-density medical imaging signal chains.

Technical Context

The DDC232CKZXGR implements a true integrating architecture with 64 on-chip switched integrators-two per channel-enabling simultaneous integration and digitization. Its front-end uses selectable on-die feedback capacitors (3–87.5 pF) controlled by Range[2:0] bits to set full-scale input from 12.5 pC to 350 pC.

It employs a delta-sigma A/D core synchronized to an external system clock (CLK) and conversion control (CONV), with internal timing ensuring precise charge reset and sampling. The device supports both continuous mode (t_INT = 166 ms to 1 s) and noncontinuous mode, and features dedicated configuration registers accessed via DIN_CFG/CLK_CFG pins.

Key Specifications

Pinout & Package

BGA-64 package (7 mm × 7 mm, 0.8 mm pitch) with 32 analog inputs (IN1–IN32), dual ground planes (AGND/DGND), separate AVDD (5 V) and DVDD (3.3 V) supplies, and dedicated serial interface pins for daisy-chained multi-device systems.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar current-input ADC applications.

Compared with DDC232CZXR and ADAS1000-3BSTZ, the DDC232CKZXGR uniquely combines 32-channel current-input integration, 6.2 kSPS throughput, and daisy-chain scalability - making it the only option for high-channel-count, high-speed photon detection systems requiring minimal external components.

Availability

DDC232CKZXGR is available at Aetrix Electronics and suitable for CT scanner DAS, photodiode sensor arrays, and X-ray detection systems requiring stable component supply, long-lifecycle assurance, and traceable sourcing for Class II medical electronics.

Supply support for DDC232CKZXGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision data converters and medical imaging ICs.

The DDC232 family was designed specifically for direct digitization of low-level photodiode currents in computed tomography and digital radiography systems, emphasizing ultra-low noise, channel-to-channel matching, and integration-friendly packaging.

FAQ

What is the maximum data rate supported by the DDC232CKZXGR?

The DDC232CKZXGR supports a maximum data rate of 6.2 kSPS, which is the defining performance distinction versus the DDC232CZXR (3.1 kSPS). This higher rate is enabled by shorter minimum integration time (166.5 ms) and faster internal conversion logic. The DDC232CKZXGR achieves this while maintaining 5.3 ppm FSR rms noise and ±0.025% integral linearity - critical for clinical CT image quality. System clock (CLK) must be configured with Clk_4x = 1 to support 20 MHz operation for full 6.2 kSPS capability.

How does the dual-switched integrator architecture improve measurement continuity in the DDC232CKZXGR?

The DDC232CKZXGR uses two independent integrators per channel (Side A and Side B) to eliminate dead time between conversions. While one side integrates incoming photodiode current, the other side is simultaneously digitized by the on-chip delta-sigma ADC. This architecture enables true continuous integration mode - essential for capturing rapidly varying X-ray flux in CT gantry rotation. The CONV pin controls side switching and must be synchronized to the CLK rising edge within ±10 ns to maintain specified noise and linearity performance in the DDC232CKZXGR.

What are the voltage reference requirements for stable operation of the DDC232CKZXGR?

The DDC232CKZXGR requires a stable +4.096 V external reference applied to VREF (pins A6/B6) to reset integrator capacitors and define full-scale range. Reference drift directly causes gain error and offset drift - TI specifies ±0.1% VREF stability over temperature for ≤1.5 ppm FSR range error. A buffered reference circuit using a low-noise op amp (e.g., OPA350) and RC filter is mandatory; unbuffered references introduce noise and droop during ∆Σ conversion, degrading DDC232CKZXGR's 5.3 ppm noise floor and causing up to ±1000 ppm offset error.

Can multiple DDC232CKZXGR devices be connected in series, and what interface signals are required?

Yes, the DDC232CKZXGR supports daisy-chained configuration using its dedicated serial interface: DIN connects to upstream DOUT, while DCLK, DVALID, CLK, and CONV are shared across all devices. Only DIN_CFG, CLK_CFG, and RESET require individual control per device for configuration. This topology reduces FPGA I/O count and simplifies PCB routing in multi-module CT detector systems. Up to 8 DDC232CKZXGR devices can be cascaded without timing degradation, provided DCLK skew is minimized (<1 ns) and common-mode noise on shared clocks is suppressed with proper grounding.

What is the significance of the 'K' suffix in DDC232CKZXGR, and how does it affect thermal design?

The 'K' in DDC232CKZXGR denotes the high-speed variant: it delivers 6.2 kSPS (vs. 3.1 kSPS for 'C') at 10 mW/channel (290 mW total), compared to 7 mW/channel (224 mW) for DDC232CZXR. This 30% higher power dissipation requires careful thermal management in densely packed detector modules. TI specifies 0°C to +70°C operation, but junction temperature must remain ≤125°C. Recommended layout includes 4+ internal copper layers, thermal vias under the BGA-64 package, and connection of all AGND/DGND pads to solid ground planes - critical to maintain DDC232CKZXGR's specified noise and linearity performance.