Texas Instruments DDC232CKZXGT

Overview

DDC232CKZXGT from Texas Instruments is a 20-bit, 32-channel, current-input analog-to-digital converter with dual-switched integrator front-end architecture. It delivers ±0.025% integral linearity, 5.3ppm FSR noise, and supports up to 6.2kSPS data rate at 350pC full-scale range for photodiode and X-ray sensor interfaces.

For engineers reviewing the DDC232CKZXGT datasheet, DDC232CKZXGT pinout, DDC232CKZXGT application, or DDC232CKZXGT equivalent, key selection criteria include integration time adjustability (166ms–1s), daisy-chainable serial interface, and low 10mW/channel power dissipation in BGA-64 packaging.

Technical Context

The DDC232CKZXGT implements continuous-time dual-switched integrators per channel-enabling simultaneous integration on one side while digitizing the other-ensuring uninterrupted current measurement from fA to mA levels. Its delta-sigma A/D core operates synchronously with CLK and CONV timing, requiring precise ±10ns alignment between CONV rising edge and CLK for optimal noise performance.

Configuration is managed via dedicated DIN_CFG/CLK_CFG pins controlling 12-bit register settings including Range[2:0] (selecting 350pC full-scale), Format (20-bit output), Version (CK variant), and Clk_4x (4× internal clock divider enabling 20MHz CLK input). VREF stability is critical: ±0.1V variation directly impacts full-scale range accuracy and offset drift.

Key Specifications

Pinout & Package

BGA-64 package (7mm × 7mm, 0.8mm pitch) with separate AGND/DGND planes, dual VREF inputs, and dedicated configuration clock/data pins for deterministic register programming.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar current-input ADC applications.

Compared with DDC232CZXGT, DDC232CKZXGT trades 3mW/channel extra power for 2× higher throughput-ideal for fixed-installation CT systems. ADAS1000-3BSTZ lacks channel count, current-input architecture, and daisy-chain capability required for photodiode array digitization.

Availability

DDC232CKZXGT is available at Aetrix Electronics and suitable for CT scanner detector acquisition systems, photodiode-based analytical instruments, and industrial X-ray radiography equipment requiring stable component supply across multi-year production cycles.

Supply support for DDC232CKZXGT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with over 50 years of precision data converter innovation.

The DDC232CKZXGT belongs to TI's Direct Digital Current Converter family-designed specifically for high-accuracy, multi-channel current digitization in medical imaging and scientific instrumentation where photon starvation and thermal drift are primary design constraints.

FAQ

What is the maximum integration time supported by the DDC232CKZXGT?

The DDC232CKZXGT supports integration times from 166ms to 1,000ms in continuous mode. This range is set by the tINT parameter in the device's timing configuration and enables precise measurement of input currents spanning femtoamps to milliamps. The DDC232CKZXGT achieves its specified 5.3ppm FSR noise performance at 166ms integration time with 350pC full-scale range, making it suitable for high-speed CT scanner data acquisition where temporal resolution is critical.

How does the dual-switched integrator architecture in the DDC232CKZXGT improve measurement continuity?

The DDC232CKZXGT uses two independent integrators per channel-Side A and Side B-that operate alternately under CONV control. While one side integrates incoming current, the other is digitized by the onboard delta-sigma converter. This architecture eliminates dead time between conversions, enabling truly continuous current measurement essential for pulsed X-ray sources. The DDC232CKZXGT maintains this continuity even at its maximum 6.2kSPS data rate, ensuring no signal dropout during rapid photon flux changes.

What are the voltage reference requirements for stable operation of the DDC232CKZXGT?

The DDC232CKZXGT requires a stable +4.096V external reference applied to both VREF pins (A6 and B6), with tolerance of ±0.1V. Reference instability directly impacts full-scale range accuracy and offset drift-±0.1V deviation introduces ~2.5% gain error. TI recommends buffering VREF with a low-noise op-amp (e.g., OPA350) and filtering with a 0.47µF capacitor, as shown in Figure 6 of the SBAS331D datasheet. The DDC232CKZXGT draws up to 650mA average reference current at 166ms integration time, necessitating a robust reference source capable of sustained current delivery.

Can multiple DDC232CKZXGT devices be synchronized in a daisy-chain configuration?

Yes, the DDC232CKZXGT supports hardware daisy-chaining via its dedicated serial interface: DOUT of one device connects to DIN of the next, with shared CLK and DCLK signals across all units. This configuration allows synchronous sampling of up to 32×N channels using a single FPGA interface. The DDC232CKZXGT's DVALID signal remains aligned across the chain, enabling coordinated readout without additional synchronization logic. Configuration registers are written individually using DIN_CFG/CLK_CFG pins, preserving independent range and format settings per device.

What is the significance of the Clk_4x bit in the DDC232CKZXGT configuration register?

The Clk_4x bit (bit 6) in the DDC232CKZXGT configuration register enables an internal 4× clock divider, allowing the device to accept a 20MHz system clock (CLK) while operating its internal timing at 5MHz. This provides finer quantization of integration time and improves CONV-to-CLK alignment tolerance-critical for minimizing noise in high-precision applications. When Clk_4x = 1, the DDC232CKZXGT achieves optimal performance with 20MHz CLK input; when Clk_4x = 0, maximum CLK frequency is limited to 5MHz. The setting is non-volatile and must be programmed during initialization.