Texas Instruments DDC232CZXGR

Overview

DDC232CZXGR from Texas Instruments is a 20-bit, 32-channel, current-input analog-to-digital converter with dual-switched integrator front-end architecture. It directly digitizes low-level photodiode currents (down to fA range) using on-chip integration, supports adjustable full-scale ranges up to ±350 pC, delivers ±0.025% integral linearity and 5.3 ppm FSR rms noise, and operates in CT scanner detector acquisition systems requiring high-precision, low-drift current measurement.

For engineers reviewing the DDC232CZXGR datasheet, DDC232CZXGR pinout, DDC232CZXGR application, or DDC232CZXGR equivalent, key selection criteria include its 32-channel current-input architecture, 7 mW/channel power dissipation, BGA-64 package with verified analog/digital ground separation, and daisy-chainable serial interface for multi-device DAS scalability.

Technical Context

The DDC232CZXGR implements continuous-time dual-switched integrators per channel-enabling simultaneous integration on one side while digitizing the other-driven by an external 1–5 MHz system clock (CLK) and synchronized CONV control. Its delta-sigma A/D core samples held integrator outputs, eliminating aliasing concerns for DC/low-frequency current signals.

Configuration is managed via dedicated DIN_CFG/CLK_CFG pins controlling a 12-bit register that sets full-scale range (8 options), output format (16-/20-bit), Clk_4x divider, and test mode. VREF (4.096 V nominal) resets integration capacitors and serves as conversion reference, demanding low-noise buffering per TI's recommended circuit.

Key Specifications

Pinout & Package

The DDC232CZXGR is housed in a 64-pin BGA package (10 mm × 10 mm, 0.8 mm pitch) with defined analog/digital power and ground segregation. Pin assignments follow TI's standardized top-view layout with dedicated quiet analog ground (QGND), multiple AGND/DGND ties, and isolated VREF input.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar current-input ADC applications.

Compared with DDC232CKZXGR, the DDC232CZXGR trades 2× lower data rate for 30% lower power and 2× longer integration time-directly enabling 5.3 ppm noise performance unattainable in the CK variant. Against ADAS1000-3BSTZ, it offers 6.4× more channels and true fA-level current-input sensitivity, but no embedded biopotential features.

Availability

DDC232CZXGR is available at Aetrix Electronics and suitable for CT scanner detector acquisition systems, photodiode array readout modules, and X-ray flat panel detector designs requiring stable component supply, long-term production continuity, and traceable sourcing from authorized channels.

Supply support for DDC232CZXGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, medical, and automotive applications.

The DDC232CZXGR belongs to TI's precision current-input ADC product line, engineered specifically for direct digitization of low-level photodiode and scintillator currents in medical imaging and scientific instrumentation.

FAQ

What is the maximum integration time supported by the DDC232CZXGR?

The DDC232CZXGR supports a maximum integration time of 1,000,000 ms (1 second) in continuous mode. This extended integration window enables ultra-low-noise operation down to 5.3 ppm of full-scale range, making the DDC232CZXGR ideal for high-precision, low-speed current measurement applications such as static CT calibration or low-flux photon counting. The device maintains specified accuracy and linearity across the full 320 ms to 1 s range.

Does the DDC232CZXGR require external integration capacitors?

No, the DDC232CZXGR does not require external integration capacitors. It integrates seven factory-trimmed capacitor values (3–87.5 pF) on-die for both sides of all 32 channels. These capacitors are selected via the 3-bit Range[2:0] field in the configuration register, enabling full-scale ranges from ±12.5 pC to ±350 pC without external components-reducing BOM count and layout complexity while ensuring channel-to-channel matching.

How is the DDC232CZXGR configured for different full-scale ranges?

The DDC232CZXGR is configured for eight full-scale ranges using the 3-bit Range[2:0] field (bits 11–9) in its 12-bit configuration register. Writing values 000 through 111 selects corresponding on-chip integration capacitors, yielding nominal full-scale ranges from ±12.5 pC to ±350 pC. Configuration is performed via DIN_CFG and CLK_CFG pins; the setting applies uniformly to all 32 channels and both integrator sides per channel.

What is the role of the QGND pin on the DDC232CZXGR?

The QGND pin (located at H5) on the DDC232CZXGR provides a dedicated quiet analog ground connection for the most noise-sensitive analog circuitry, including the integrator op-amps and reference buffer inputs. Unlike standard AGND pins, QGND is internally isolated to minimize voltage fluctuations caused by digital switching currents, thereby preserving the 5.3 ppm noise floor and ±0.025% linearity specifications of the DDC232CZXGR in high-resolution medical imaging applications.

Can multiple DDC232CZXGR devices be synchronized in a single system?

Yes, multiple DDC232CZXGR devices can be fully synchronized using a common system clock (CLK) and shared CONV signal. The daisy-chainable serial interface allows cascading DOUT→DIN connections while maintaining phase alignment across all units. TI specifies that CONV must toggle within ±10 ns of the CLK rising edge for optimal noise performance-achievable with matched trace lengths and a centralized clock distribution network in multi-device DAS architectures.