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Texas Instruments DDC264CKZAW
- Part No.:
- DDC264CKZAW
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 100-LFBGA
- Datasheet:
-
DDC264CKZAW.pdf
- Description:
- IC ADC 20BIT SIG-DELTA 100NFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,915
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Product details
Overview
DDC264CKZAW from Texas Instruments is a 20-bit, 64-channel, current-input analog-to-digital converter with dual switched integrator architecture. It directly digitizes low-level photodiode currents (fA to µA range) using on-chip integration and multiplexed ADC conversion, delivering ±0.025% INL and 6.3 ppm FSR noise at 6.2 kSPS in CT scanner DAS and X-ray detection systems.
For engineers reviewing the DDC264CKZAW datasheet, DDC264CKZAW pinout, DDC264CKZAW application, or DDC264CKZAW equivalent, key selection criteria include its 100-pin NFBGA package, 160–1,000,000 µs adjustable integration time, 5.5 mW/channel power dissipation, and daisy-chainable serial interface supporting multi-device synchronization without added digital overhead.
Technical Context
The DDC264CKZAW implements a continuous-time dual-integrator front end: while one integrator (Side A or B) integrates input current, the other is simultaneously digitized by the onboard 20-bit ADC. Integration is controlled by the external CONV signal synchronized to CLK's falling edge (±10 ns tolerance), enabling lossless charge collection and stable offset performance.
It supports four full-scale ranges (12.5 pC to 150 pC) via internal trimmed capacitors (3–37.5 pF), selectable via Range[1:0] bits. The device uses separate analog (AVDD = 5 V) and digital (DVDD = 2.7–3.6 V) supplies, with dedicated QGND for quiet analog reference and AGND/DGND isolation to minimize coupling noise in high-precision current measurement.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 20-bit straight-binary output with no missing codes - ensures unambiguous quantization of ultra-low current signals across full dynamic range. |
| Data Rate | 6.25 kSPS maximum - enables real-time acquisition in high-speed medical imaging systems such as CT detector arrays. |
| INL Error | ±0.025% of reading ±1 ppm of FSR - guarantees sub-ppm linearity critical for quantitative photon counting and dose calibration. |
| Input Noise | 6.3 ppm of FSR rms (Range 3, CSENSOR = 35 pF) - corresponds to 0.72 fC rms noise floor, supporting femtoampere-level signal integrity. |
| Integration Time | Adjustable from 160 µs to 1 s - allows optimization for signal amplitude and bandwidth trade-offs in photodiode or ion chamber interfaces. |
| Power per Channel | 5.5 mW at max data rate - enables dense channel count (64) in thermally constrained medical and industrial sensor modules. |
| Supply Voltages | AVDD = 4.9–5.1 V; DVDD = 2.7–3.6 V - strict analog rail tolerance ensures reference stability and minimizes gain drift in precision current-to-digital conversion. |
Pinout & Package
The DDC264CKZAW is housed in a 100-pin NFBGA (ZAW) package measuring 9.00 mm × 9.00 mm, with exposed thermal pad and fine-pitch 0.5-mm ball pitch. Pin functions are defined per TI SBAS368D Rev. D, including dedicated quiet analog ground (QGND), dual ground domains (AGND/DGND), and separate configuration/data clock paths (CLK_CFG/DCLK).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1–IN64 | Analog input | 64 independent current-sink inputs accepting fA–µA photodiode or sensor currents; each routed to dual integrators for continuous sampling. |
| CONV | Digital input | Edge-triggered control signal toggling integration between Side A and Side B; must be synchronized to CLK falling edge for optimal noise performance. |
| DVALID | Digital output | Active-low strobe indicating valid 20-bit data ready in shift register; timing-critical for synchronous readout in daisy-chained systems. |
| DOUT / DIN / DCLK / DIN_CFG / CLK_CFG | Digital I/O | Separate serial data path (DOUT/DIN/DCLK) for measurement data and dedicated config path (DIN_CFG/CLK_CFG) for register programming - prevents interference between acquisition and setup. |
| QGND | Analog ground | Low-noise quiet ground for integrator op-amps and reference circuitry; requires isolated PCB pour and star connection to minimize switching noise coupling. |
| VREF | Analog input | 4.096-V external reference input; sets full-scale charge range and directly impacts gain accuracy - must be low-drift, low-noise, and bypassed locally. |
Key Features
| Feature | Design Value |
|---|---|
| Dual switched integrator architecture | Enables continuous current integration with zero dead time - eliminates sampling gaps that cause aliasing or missed events in pulsed radiation detection. |
| On-chip integration capacitors | Four factory-trimmed values (3–37.5 pF) selectable per channel - eliminates external capacitor matching and layout sensitivity while ensuring <0.5% range error match across all 64 channels. |
| Daisy-chainable serial interface | Single DOUT→DIN cascade across multiple DDC264CKZAW devices with common CLK/CONV - reduces FPGA I/O count and simplifies timing in multi-sensor array designs. |
| In-package bypass capacitance | Integrated ceramic capacitors reduce external component count and PCB area - improves power supply rejection and stabilizes AVDD/DVDD during high-current switching transients. |
| Separate analog/digital grounds and supplies | AGND/QGND/DGND and AVDD/DVDD isolation - suppresses digital switching noise from corrupting ultra-low-current analog integration paths. |
Applications
| CT Scanner Detector Array | Photodiode Sensor Array |
|---|---|
Use Scenario: Digitizing current outputs from 64 scintillator-photodiode pairs in a single CT detector module under high-flux X-ray exposure. IC Role / Device Role / Timing Role: Primary current-input ADC performing simultaneous integration and digitization of all 64 channels with synchronized CONV/CLK timing. Use Value: 6.25 kSPS throughput and 6.3 ppm FSR noise enable accurate photon counting and dose mapping without frame averaging or external amplification. |
Use Scenario: High-density optical sensing in industrial inspection systems using 64-element linear photodiode arrays for defect detection. IC Role / Device Role / Timing Role: Direct current-to-digital conversion front end with programmable integration time to adapt to varying light intensity and ambient conditions. Use Value: Adjustable 160 µs–1 s integration and 20-bit resolution support both fast transient capture and low-light integration without signal clipping or quantization loss. |
| X-Ray Detection System | Ion Chamber Readout |
Use Scenario: Real-time acquisition of ionization current from multi-segment X-ray detectors in security or non-destructive testing equipment. IC Role / Device Role / Timing Role: Precision integrating ADC converting picoampere-level ion currents into calibrated digital values with traceable linearity. Use Value: ±0.025% INL and ±1 ppm FSR offset drift ensure long-term calibration stability required for regulatory-compliant radiation measurement. |
Use Scenario: Low-power, high-accuracy readout of ion chamber leakage current in environmental radiation monitors operating continuously for months. IC Role / Device Role / Timing Role: Ultra-low-noise current digitizer with 5.5 mW/channel power enabling battery or energy-harvesting operation. Use Value: 0.72 fC rms noise floor and 3 mW/channel (DDC264C variant) or 5.5 mW/channel (DDC264CK) support >1-year field deployment without recalibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar current-input ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DDC264CZAW | Lower max data rate (3.125 kSPS vs 6.25 kSPS); lower power (3 mW/channel vs 5.5 mW); longer min integration time (320 µs vs 160 µs) | Better suited for low-bandwidth, ultra-low-power applications where thermal budget or battery life dominates over speed | Select DDC264CZAW when system sampling requirements are ≤3 kSPS and power-per-channel must be minimized. |
| DDC1128ZAW | 128-channel version; same 6.25 kSPS max rate and 150 pC full-scale range; higher total power (5.5 mW/channel) but double channel density | Enables higher spatial resolution in detector arrays without increasing board area or interconnect complexity | Choose DDC1128ZAW when scaling beyond 64 channels is required and PCB space is constrained. |
Compared with DDC264CZAW, the DDC264CKZAW trades 2× higher power for 2× faster acquisition - essential for motion-artifact-free CT imaging. Compared with DDC1128ZAW, it offers identical per-channel performance at half the channel count, simplifying layout and reducing inter-channel crosstalk risk in smaller arrays.
Availability
DDC264CKZAW is available at Aetrix Electronics and suitable for CT scanner DAS, photodiode sensor arrays, X-ray detection systems, and ion chamber readout requiring stable component supply across multi-year medical device production cycles.
Supply support for DDC264CKZAW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision data converters and medical imaging solutions.
The DDC264CKZAW belongs to TI's DDC (Digital Current-to-Digital Converter) family, engineered specifically for direct digitization of ultra-low-current sensors in radiation detection, medical diagnostics, and scientific instrumentation.
FAQ
What is the maximum integration time supported by the DDC264CKZAW?
The DDC264CKZAW supports an adjustable integration time ranging from 160 µs to 1,000,000 µs (1 second). This wide range allows precise adaptation to input signal amplitude and bandwidth requirements - for example, shorter times suit high-flux X-ray pulses, while longer times enhance SNR in low-light photodiode applications. The value is set via internal register configuration and is fully supported across all four full-scale ranges.
Does the DDC264CKZAW require external integration capacitors?
No, the DDC264CKZAW does not require external integration capacitors. It integrates four factory-trimmed capacitor values (3 pF, 12.5 pF, 25 pF, and 37.5 pF) on-die, selected via the Range[1:0] control bits. These capacitors are matched and trimmed to ensure <0.5% range error match across all 64 channels, eliminating layout sensitivity and external component variation that would degrade precision in discrete integrator designs.
How is daisy-chaining implemented on the DDC264CKZAW?
Daisy-chaining on the DDC264CKZAW uses separate signal paths: measurement data flows through DOUT → DIN of the next device, while shared CLK and CONV signals drive all devices synchronously. Configuration data (DIN_CFG/CLK_CFG) remains local to each device. This architecture minimizes digital overhead - only one DCLK line and one DVALID line are needed per chain - and ensures deterministic timing alignment across all 64 channels in multi-device systems.
What is the role of the QGND pin on the DDC264CKZAW?
The QGND (Quiet Analog Ground) pin on the DDC264CKZAW provides a dedicated low-noise return path for the integrator operational amplifiers and voltage reference circuitry. It must be isolated from noisy digital ground (DGND) and high-current analog ground (AGND) on the PCB, connected via a short, low-inductance trace to a clean ground plane. Proper QGND routing is essential to achieve the specified 6.3 ppm FSR noise performance and prevent digital switching noise from modulating the ultra-low-current integration process.
Can the DDC264CKZAW operate with a 3.3-V AVDD supply?
No, the DDC264CKZAW requires a 5-V nominal analog supply (AVDD), with a recommended operating range of 4.9 V to 5.1 V for the CK speed grade. Using 3.3 V on AVDD violates absolute maximum ratings and will prevent proper operation of the analog front end, including integrator biasing and reference scaling. The digital supply (DVDD) accepts 2.7–3.6 V, but AVDD must remain at 5 V to maintain specified INL, noise, and full-scale accuracy.
DDC264CKZAW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 100-LFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Number of Bits:
- 20
- Sampling Rate (Per Second):
- 6k
- Number of Inputs:
- 64
- Input Type:
- Single Ended
- Data Interface:
- SPI
- Configuration:
- ADC
- Ratio - S/H:ADC:
- -
- Number of A/D Converters:
- 32
- Architecture:
- Sigma-Delta
- Reference Type:
- External
- Voltage - Supply, Analog:
- 5V
- Voltage - Supply, Digital:
- 2.7V ~ 5.25V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 100-NFBGA (9x9)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
DDC264CKZAW FAQ
1.How can I place an order for DDC264CKZAW through Aetrix?
Please submit a Request for Quotation (RFQ) for DDC264CKZAW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DDC264CKZAW reliable?
The price and inventory of DDC264CKZAW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DDC264CKZAW is usually 5 days.
3.What payment methods are accepted for DDC264CKZAW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DDC264CKZAW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DDC264CKZAW?
DDC264CKZAW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DDC264CKZAW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DDC264CKZAW?
For technical support, including DDC264CKZAW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DDC264CKZAW requirements.
6.How does Aetrix verify that DDC264CKZAW is sourced from the original manufacturer or authorized distributors?
All DDC264CKZAW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DDC264CKZAW meets industry standards.
7.What is the process for return or replacement of DDC264CKZAW?
All DDC264CKZAW units undergo pre-shipment inspection (PSI). If there is an issue with DDC264CKZAW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DDC264CKZAW part is unused and in its original packaging.
Return procedure for DDC264CKZAW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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