Texas Instruments DEM-ADS807E

Overview

DEM-ADS807E from Burr-Brown (now Texas Instruments) is an evaluation fixture designed specifically for the ADS807E 12-bit, 53MHz analog-to-digital converter. It supports single-ended or differential input configurations, external TTL clocking via SMA J1, ±5V analog/digital power supplies, and offers flexible front-end options including active op-amp (OPA642N), passive transformer (TT1-6), or buffered signal paths.

For engineers reviewing the DEM-ADS807E datasheet, DEM-ADS807E pinout, DEM-ADS807E application, or DEM-ADS807E equivalent, this board enables rapid performance validation of high-speed ADC interface design, clock jitter sensitivity, reference selection (internal/external), full-scale range configuration (2V_p-p/3V_p-p), and CMOS data output timing with FCT541 buffering.

Technical Context

The DEM-ADS807E implements a four-layer PCB layout with dedicated analog ground plane, surface-mount construction, and strategic decoupling (e.g., 10µF tantalum + 0.1µF ceramic per supply rail) to preserve ADS807E's 53MHz sampling integrity. Clock input at J1 presents a 50Ω load and requires low-jitter TTL-level signals (≥+2.7V HIGH, optimal +3V with ≤1µs edge times).

Signal conditioning supports three distinct input topologies: ac-coupled differential (via dual OPA642N amplifiers), transformer-coupled differential (using Mini-Circuits TT1-6), or dc-coupled single-ended (with R30 jumper). Full-scale range selection is controlled by logic level on ADS807E pin 15 (RSEL), and common-mode bias is derived from internal references unless INT/EXT switch is opened for external reference operation.

Key Specifications

Availability

DEM-ADS807E is available at Aetrix Electronics and suitable for high-speed data acquisition system development, ADC interface validation, clock jitter characterization, and RF-sampling prototype testing requiring stable component supply and documented reference design fidelity.

Supply support for DEM-ADS807E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Burr-Brown Corporation, acquired by Texas Instruments in 2000, specialized in precision analog and high-speed data conversion ICs before integration into TI's Data Converters product line.

The DEM-ADS807E belongs to Burr-Brown's legacy evaluation fixture family, engineered to accelerate design-in of their high-performance ADCs-specifically enabling lab-based validation of dynamic performance, layout-sensitive signal integrity, and system-level timing margins.

FAQ

What is the primary purpose of the DEM-ADS807E?

The DEM-ADS807E is an evaluation fixture built exclusively to characterize the ADS807E 12-bit, 53MHz analog-to-digital converter. It provides configurable signal paths, clocking, power delivery, and data capture infrastructure - not a functional subsystem or production-ready module. The DEM-ADS807E enables measurement of SNR, SFDR, and ENOB under real-world layout and drive conditions.

Does the DEM-ADS807E include the ADS807E IC?

Yes, the DEM-ADS807E evaluation fixture includes one ADS807E IC (28-lead SSOP) mounted as U1 on the board. The fixture is delivered fully assembled with the ADS807E installed, along with supporting components like OPA642N op amps, IDT74FCT541T buffers, and passive network elements required for baseline operation.

Can the DEM-ADS807E operate with an external reference voltage?

Yes, the DEM-ADS807E supports external reference operation. To enable it, open the INT/EXT solder switch, close JP3 and JP4, and apply the external reference voltage to connector P3. The selected reference determines the full-scale input range, and must comply with ADS807E's specified external reference voltage limits per its datasheet.

What clock signal requirements apply to the DEM-ADS807E?

The DEM-ADS807E requires an external TTL clock applied to SMA connector J1. The input presents a 50Ω load. For valid performance evaluation - especially undersampling - the clock source must exhibit very low jitter. Logic HIGH must be ≥+2.7V; +3V with ≤1µs rise/fall times is recommended for optimal DEM-ADS807E results.

How is the input full-scale range selected on the DEM-ADS807E?

The DEM-ADS807E uses the ADS807E's RSEL pin (pin 15) to select full-scale input range: 2V_p-p (default, internal pulldown) or 3V_p-p (logic HIGH). This is implemented via a dedicated solder switch on the DEM-ADS807E board - closing the RSEL switch applies +5V to pin 15, configuring the ADS807E for 3V_p-p operation.