Texas Instruments DEM-ADS9XXE

Overview

DEM-ADS9XXE from Texas Instruments is an evaluation module designed to demonstrate and validate the ADS900E 10-bit, 20 MSPS pipeline analog-to-digital converter. It supports single-ended and differential input configurations, features on-board clock conditioning, internal reference routing, and SSOP-28 socketed ADC placement for rapid prototyping in high-speed data acquisition systems.

For engineers reviewing the DEM-ADS9XXE datasheet, DEM-ADS9XXE pinout, DEM-ADS9XXE application, or DEM-ADS9XXE equivalent, this module enables functional validation of timing-critical sampling performance, SNR/SFDR trade-offs at 500 kHz–10 MHz input frequencies, and power-down behavior under +3V supply operation - critical for IF sampling, portable test equipment, and video digitization designs.

Technical Context

The DEM-ADS9XXE implements a complete signal chain around the ADS900E, including a low-jitter clock driver (supporting 20 MHz sampling), configurable input termination (50 Ω/75 Ω/1 kΩ), and selectable common-mode biasing via the ADS900E's CM, LpBy, and LnBy pins. It routes all 10 digital output bits with controlled impedance traces and provides dedicated LVDD decoupling separate from analog +VS.

Board-level design enforces strict analog/digital partitioning: analog ground planes are isolated from digital return paths, and the ADS900E's SSOP-28 socket is surrounded by 0.1 µF ceramic bypass capacitors at each +VS and LVDD pin per TI SBAS058A recommendations. Power-down and OE control lines are brought out to headers for external logic sequencing.

Key Specifications

Availability

DEM-ADS9XXE is available at Aetrix Electronics and suitable for portable instrumentation, IF/baseband communications, cable modems, and set-top boxes requiring stable component supply during proof-of-concept and pre-production validation phases.

Supply support for DEM-ADS9XXE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-performance data conversion technologies. Its precision data converter portfolio serves demanding applications in test & measurement, communications, and imaging.

The DEM-ADS9XXE belongs to TI's high-speed ADC evaluation platform family, engineered specifically to accelerate system-level validation of pipeline ADCs operating at 10–20 MSPS with internal references and wideband track-and-hold front-ends.

FAQ

What is the primary function of the DEM-ADS9XXE evaluation module?

The DEM-ADS9XXE evaluation module is a hardware platform designed exclusively to evaluate the ADS900E 10-bit, 20 MSPS pipeline analog-to-digital converter. It provides full access to all ADS900E pins, implements TI-recommended decoupling and grounding, and supports both single-ended and differential input configurations per SBAS058A specifications. The DEM-ADS9XXE enables engineers to verify dynamic performance metrics - including SFDR, SNR, and aperture jitter - without custom PCB development.

Does the DEM-ADS9XXE support differential input operation for the ADS900E?

Yes, the DEM-ADS9XXE supports differential input operation for the ADS900E using an optional RF transformer interface, as described in TI SBAS058A Figure 5. The board provides dedicated SMA inputs and routing to ADS900E pins IN (27) and IN (24), along with direct access to the CM (26), LpBy (21), and LnBy (25) pins required to bias the differential pair at +1.5 V. This configuration delivers measurable SFDR and THD improvements over single-ended use.

Can the DEM-ADS9XXE be used to validate power-down functionality of the ADS900E?

Yes, the DEM-ADS9XXE exposes the Pwrdn pin (17) of the ADS900E to a header, enabling direct TTL/CMOS-level control of power-down mode. When asserted high, the ADS900E reduces supply current by ~70% and places digital outputs in high-impedance state - behavior confirmed in SBAS058A Electrical Characteristics table. The DEM-ADS9XXE's layout preserves signal integrity during transition, allowing accurate measurement of power-down enable/disable timing (133 ns / 18 ns).

What clock requirements must be met when using the DEM-ADS9XXE with the ADS900E?

The DEM-ADS9XXE accepts external CMOS-level clock signals up to 20 MHz via SMA input. To achieve rated ADS900E performance - especially SNR >45 dB at 10 MHz input - the clock must exhibit ≤2 ns rise/fall time and ≤±10% duty cycle variation, as specified in SBAS058A Clock Input Requirements. Jitter below 7 ps rms is recommended to avoid aperture jitter limiting SNR, per Equation (4) in the datasheet.

Is the DEM-ADS9XXE compatible with other ADS9xx-series ADCs beyond the ADS900E?

No, the DEM-ADS9XXE is specifically designed for the ADS900E in SSOP-28 package and is not mechanically or electrically compatible with other ADS9xx variants. Pin assignments, reference voltage levels (+1.25 V / +1.75 V), and timing parameters (5-cycle latency, 20 MSPS max) are unique to the ADS900E. Substituting other devices - even pin-compatible family members - risks incorrect biasing, timing violation, or damage due to mismatched internal architecture.