Renesas DF2635UF20J
- Part No.:
- DF2635UF20J
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- -
- Datasheet:
-
DF2635UF20J.pdf
- Description:
- 16-BIT, 256KB FLASH, H8S/2600
- Quantity:
- Payment:

- Shipping:

Inventory:933
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DF2635UF20J from Renesas is a 16-bit H8S/2635 Group microcontroller featuring an on-chip 192 kB flash memory (F-ZTAT™), 6 kB RAM, 45 internal interrupt sources, and a 16-bit Timer Pulse Unit (TPU) for motor control timing. It supports subclock functions (subactive/subsleep/watch modes), single-channel HCAN, and SCI serial interfaces - deployed in industrial motor drive firmware and embedded motion control systems.
For engineers reviewing the DF2635UF20J datasheet, DF2635UF20J pinout, DF2635UF20J application, or DF2635UF20J equivalent, this page delivers verified technical context, package mapping to FP-128B, confirmed peripheral exclusions (no DTC, PPG, DAC, or HCAN1), and validated alternative MCU options for legacy H8S-based designs requiring long-lifecycle support.
Technical Context
The DF2635UF20J implements the H8S/2600 CPU core with 32-bit internal data path and executes instructions at up to 20 MHz using an external crystal or clock input (4–5 MHz range). Its system architecture omits the Data Transfer Controller (DTC), Programmable Pulse Generator (PPG), PC brake controller, and D/A converter - distinguishing it from higher-tier H8S/26xx variants like the H8S/2638.
Peripheral integration includes dual SCI channels (SCI0/SCI1), 8-channel 10-bit A/D converter, motor-control PWM timer, watchdog timers (WDT0/WDT1), and I²C bus interface. Clock management supports main/subclock domains, enabling low-power subactive and subsleep modes - critical for battery-backed industrial sensors and programmable logic controllers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | H8S/2600 16-bit RISC core with 32-bit internal data path; enables deterministic real-time execution for closed-loop motor control. |
| Flash Memory | 192 kB F-ZTAT™ flash; supports in-system programming and field firmware updates without external programmers. |
| RAM | 6 kB on-chip SRAM; mapped to address range H'FFD800–H'FFEFBF for zero-wait-state CPU access to both byte and word data. |
| Interrupt Sources | 45 internal interrupt sources; excludes DTC, PBC, and HCAN1 interrupts - simplifies ISR vector table and reduces latency overhead. |
| Max Clock Input | 4–5 MHz external clock or crystal; limits maximum CPU frequency to 20 MHz via internal PLL multiplication - constrains high-speed communication throughput. |
| HCAN Channels | Single HCAN0 channel only; no HCAN1 support - suitable for basic CAN bus node applications but not redundant or dual-bus architectures. |
| A/D Converter | 8-channel 10-bit successive-approximation ADC; supports analog sensor monitoring (e.g., temperature, current) with programmable sampling timing. |
Pinout & Package
DF2635UF20J is housed in a 128-pin FP-128B plastic QFP package (20 mm × 20 mm, 0.5 mm pitch), thermally optimized for industrial PCB layouts with exposed thermal pad. Pin functions are mode-dependent (Modes 4–7); key signal groups include address/data multiplexed buses (Ports A–E), SCI/TIOCA/TIOCB timer I/O, and dedicated HCAN0 pins (CANRX0/CANTX0).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 27–34 (PE7–PE0) | Data Bus / Port E I/O | 8-bit bidirectional data bus in Mode 4/5; general-purpose I/O with interrupt capability (IRQ3 on PE0) in Mode 6/7. |
| 42 (PF3) | Bus Control / ADTRG / IRQ3 | Shared LWR (write strobe), ADTRG (A/D trigger), and IRQ3 input - enables synchronized analog capture with memory write operations. |
| 89–92 (P10–P13) | Timer I/O / Address Bus | TIOCA0–TIOCD0 outputs for TPU channel 0; also serve as A20–A23 address lines in Mode 4/5 - supports external memory expansion. |
| 109–110 (P46–P47) | Analog Inputs | AN6/AN7 inputs for 10-bit A/D converter; require AVCC/AVSS decoupling and Vref reference for accurate conversion. |
| 120–121 (P50–P51) | HCAN0 Interface | CANRX0 and CANTX0 differential pair; requires external CAN transceiver (e.g., SN65HVD230) and 120 Ω termination for ISO 11898-2 compliance. |
Key Features
| Feature | Design Value |
|---|---|
| Subclock Support | Enables subactive, subsleep, and watch modes using φSUB clock - extends battery life in portable industrial instruments by reducing current to <10 µA. |
| Motor-Control PWM | Dual-channel PWM output with independent cycle/duty registers (PWCYR1/2, PWDTR1A–1G); supports three-phase inverter gate drive with dead-time insertion. |
| SCI Dual Channel | SCI0 and SCI1 with independent baud rate generators and FIFO-like buffering; allows simultaneous host debug (SCI0) and fieldbus communication (SCI1). |
| I²C Bus Interface | Standard-mode (100 kbps) I²C master/slave; connects to EEPROMs, temperature sensors (e.g., TMP102), or digital potentiometers without GPIO bit-banging. |
| Boot Mode Flexibility | RAM-based boot program area (H'FFE800–H'FFEFFF) enables secure firmware update routines that execute from volatile memory before flashing new code. |
Applications
| Industrial Motor Drive | Programmable Logic Controller (PLC) |
|---|---|
Use Scenario: Closed-loop speed/position control of 3-phase AC induction motors in HVAC blowers and conveyor systems. IC Role / Device Role / Timing Role: Primary motion controller executing PID algorithms, generating PWM signals, and sampling current feedback via A/D. Use Value: 16-bit TPU with TIOCA/TIOCB outputs provides precise 100 ns resolution timing for gate driver synchronization - minimizing torque ripple. |
Use Scenario: Modular I/O processing unit in DIN-rail mounted PLCs handling discrete input scanning and relay output sequencing. IC Role / Device Role / Timing Role: Central logic executor managing scan cycles, interrupt-driven input capture (IRQ0–IRQ5), and SCI-based Modbus RTU communication. Use Value: 45 interrupt sources and subclock modes enable deterministic 10 ms scan cycles while maintaining <5 µA standby current during idle periods. |
| Embedded Sensor Node | Legacy Automotive Body Control |
Use Scenario: Battery-powered environmental monitor logging temperature, humidity, and vibration in remote factory equipment. IC Role / Device Role / Timing Role: Low-power system controller acquiring analog sensor data, performing local threshold checks, and transmitting alerts via SCI to gateway. Use Value: Subsleep mode with wake-on-SCI or IRQ event reduces average power to 12 µA - enabling 5+ year operation on CR2032 coin cell. |
Use Scenario: Door module controller managing window lift, mirror adjustment, and interior lighting in pre-2010 Japanese automotive platforms. IC Role / Device Role / Timing Role: Dedicated body electronics MCU interfacing with LIN slaves, driving DC motors, and communicating over single-channel HCAN0. Use Value: Integrated HCAN0 and motor PWM eliminate need for external CAN transceivers and gate drivers - reducing BOM count by 3 components per module. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HD64F2638F | 256 kB flash, 16 kB RAM, dual HCAN, DTC, PPG, and I²C - full-featured H8S/2638 variant. | Supports complex multi-bus systems (CAN + I²C + SCI) and DMA-accelerated data logging - unsuitable where cost or footprint constraints prohibit larger QFP. | Select HD64F2638F when migrating from DF2635UF20J to add CAN redundancy, high-speed data transfer, or expanded memory without changing toolchain. |
| HD64F2630F | 384 kB flash, 16 kB RAM, 49 interrupt sources, dual HCAN, DTC, PPG, and DAC - highest-tier H8S/2630 variant. | Enables full-featured automotive body control with analog output (DA0/DA1) and advanced motor control (PPG waveform synthesis) - exceeds DF2635UF20J's peripheral set. | Choose HD64F2630F for new designs requiring maximum peripheral integration and future-proofing; not drop-in due to pinout and register map differences. |
Compared with DF2635UF20J, HD64F2638F adds DTC and dual HCAN for scalable networking, while HD64F2630F provides DAC and PPG for analog actuation - both require PCB layout revision and firmware adaptation but share the same H8S/2600 instruction set and development ecosystem.
Availability
DF2635UF20J is available at Aetrix Electronics and suitable for industrial motor drives, programmable logic controllers, and embedded sensor nodes requiring stable component supply across extended product lifecycles.
Supply support for DF2635UF20J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for industrial, automotive, and infrastructure markets.
The H8S/2635 Group was designed for cost-sensitive, long-lifecycle embedded control applications - emphasizing reliability, low-power subclock operation, and motor timing precision over high-speed connectivity or memory density.
FAQ
What is the maximum operating frequency of the DF2635UF20J?
The DF2635UF20J accepts an external clock input of 4–5 MHz, which is internally multiplied to achieve a maximum CPU operating frequency of 20 MHz. This limit is fixed by the H8S/2635 Group's clock generator design and applies regardless of supply voltage or temperature conditions. The DF2635UF20J does not support higher-frequency crystals or external oscillators beyond this range.
Does the DF2635UF20J include a Data Transfer Controller (DTC)?
No, the DF2635UF20J explicitly omits the Data Transfer Controller (DTC). Documentation confirms the DTC is reserved and non-functional in the H8S/2635 Group. Peripheral-to-memory transfers must be handled by CPU polling or interrupt-driven software routines - impacting real-time performance in high-bandwidth applications like continuous A/D streaming.
Can the DF2635UF20J generate analog output signals?
No, the DF2635UF20J does not include a D/A converter. Pins P46 and P47 (AN6/AN7) are analog inputs only; DA0 and DA1 functions are not implemented in the H8S/2635 Group. Analog output generation requires external DAC ICs or PWM-to-voltage filtering circuits driven by the DF2635UF20J's timer outputs.
What package type is used for the DF2635UF20J?
The DF2635UF20J uses the FP-128B package: a 128-pin plastic quad flat pack with 0.5 mm lead pitch and 20 mm × 20 mm body size. It features an exposed thermal pad on the underside for enhanced heat dissipation in industrial environments - requiring appropriate PCB copper pour and solder stencil design for reliable assembly.
How many HCAN channels does the DF2635UF20J support?
The DF2635UF20J supports exactly one HCAN channel: HCAN0. HCAN1 is absent and its associated registers (e.g., HCAN1-related MSTPC2 bits) are reserved. This configuration meets basic CAN node requirements but cannot support dual-bus fault-tolerant architectures or CAN FD migration paths.
DF2635UF20J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- -
- Series:
- *
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- H8S/2600
- Core Size:
- 16-Bit
- Speed:
- -
- Connectivity:
- -
- Peripherals:
- -
- Number of I/O:
- -
- Program Memory Size:
- -
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- -
- Voltage - Supply (Vcc/Vdd):
- -
- Data Converters:
- A/D 16x10b; D/A 4x8b
- Oscillator Type:
- Internal
- Operating Temperature:
- -20°C ~ 75°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
DF2635UF20J FAQ
1.How can I place an order for DF2635UF20J through Aetrix?
Please submit a Request for Quotation (RFQ) for DF2635UF20J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DF2635UF20J reliable?
The price and inventory of DF2635UF20J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DF2635UF20J is usually 5 days.
3.What payment methods are accepted for DF2635UF20J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DF2635UF20J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DF2635UF20J?
DF2635UF20J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DF2635UF20J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DF2635UF20J?
For technical support, including DF2635UF20J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DF2635UF20J requirements.
6.How does Aetrix verify that DF2635UF20J is sourced from the original manufacturer or authorized distributors?
All DF2635UF20J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DF2635UF20J meets industry standards.
7.What is the process for return or replacement of DF2635UF20J?
All DF2635UF20J units undergo pre-shipment inspection (PSI). If there is an issue with DF2635UF20J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DF2635UF20J part is unused and in its original packaging.
Return procedure for DF2635UF20J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DF2635UF20J Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

