Vishay Siliconix DG181AP
- Part No.:
- DG181AP
- Manufacturer:
- Vishay Siliconix
- Package:
- 14-DIP (0.300", 7.62mm)
- Datasheet:
-
DG181AP.pdf
- Description:
- IC SWITCH SPST-NCX2 30OHM 14DIP
- Quantity:
- Payment:

- Shipping:

Inventory:4,673
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Product details
Overview
DG181AP from Vishay Siliconix is a radiation-hardened, dual SPST JFET analog switch optimized for precision audio/video signal routing in aerospace and defense systems. It features 30 Ω typical on-resistance (rDS(on)), <2 nA channel-on leakage (ID(on)), 150 ns max turn-off time, ±15 V analog signal range (–7.5 V to +15 V), and operates across –55 °C to +125 °C. Used in guidance control systems requiring low distortion and flat resistance over full signal swing.
For engineers reviewing the DG181AP datasheet, DG181AP pinout, DG181AP application, or DG181AP equivalent, this page delivers verified military-grade specifications, validated 14-pin sidebraze package details, confirmed TTL-compatible logic interface behavior, and direct alternatives for high-reliability analog switching in harsh-environment designs.
Technical Context
The DG181AP integrates four n-channel JFETs with a bipolar TTL-compatible driver to achieve bidirectional conduction in both ON states and 20 V peak-to-peak blocking capability in OFF states. Its constant rDS(on) over the full analog range eliminates large-signal errors in precision sample/hold and video gain-setting circuits.
Designed for MIL-PRF-38535 Class B compliance, it supports three independent supply domains: analog (V+/V–), logic (VL), and reference (VR), with strict isolation limits-e.g., VL to VR ≤ 8 V, VR to VIN ≤ 2 V-to prevent latch-up and ensure fault tolerance in mixed-signal avionics subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| rDS(on) | 30 Ω max at IS = –10 mA, VD = –7.5 V - ensures minimal signal attenuation and gain error in DC-coupled video/audio paths |
| ID(on) | –200 nA max at VD = VS = 7.5 V - guarantees sub-LSB error in 16-bit data acquisition front-ends |
| ton / toff | 180 ns / 150 ns max - enables reliable switching of NTSC/PAL composite video signals without visible artifacts |
| OIRR | >50 dB at 1 MHz, RL = 75 Ω - provides strong channel-to-channel isolation in multi-source video matrix applications |
| Analog Range | –7.5 V to +15 V - supports rail-to-rail operation with ±12 V op-amp interfaces and legacy military signal levels |
| Supply Range | V+ to V– = 36 V - allows flexible biasing in wide-input power architectures common in airborne radar receivers |
| Temp Range | –55 °C to +125 °C - qualified for operation in engine bay, missile seeker, and satellite payload environments |
Pinout & Package
Package: 14-pin sidebraze metal can (hermetically sealed, MIL-STD-1835 compliant), suitable for high-vibration and vacuum environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | S1, S2, D1, D2 | Switch source/drain terminals - bidirectional analog I/O; each pair forms one SPST switch path |
| 5–8 | NC | No-connect pins - electrically isolated; must remain unconnected per MIL-PRF-38535 design rules |
| 9, 12 | IN1, IN2 | TTL-compatible digital inputs - drive internal bipolar logic; accept 0.8 V low / 2.0 V high thresholds |
| 10, 11 | V–, V+ | Analog supply rails - establish switch conduction window; require decoupling near package for EMI immunity |
| 13, 14 | VL, VR | Logic (5 V) and reference (GND) supplies - isolate digital control domain from analog signal path to suppress ground bounce |
Key Features
| Feature | Design Value |
|---|---|
| Constant rDS(on) | 30 Ω max across full –7.5 V to +15 V analog range - eliminates harmonic distortion in audio mixing and video gain control |
| Radiation Hardness | Qualified per MIL-PRF-38535 Class B - withstands ≥100 krad(Si) TID and meets SEL immunity requirements for LEO missions |
| Low Charge Injection | <1 pC typical - prevents voltage spikes at output during switching, critical for precision sample-and-hold hold capacitor stability |
| High Off Isolation | >50 dB @ 1 MHz - maintains signal integrity when routing multiple video sources to shared display hardware |
| Triple Supply Independence | V+, V–, VL, VR fully isolated - enables separate grounding and filtering for analog, logic, and reference domains in noise-sensitive RF front-ends |
Applications
| Guidance & Control Systems | Video Signal Routing |
|---|---|
Use Scenario: Selecting between inertial measurement unit (IMU) and GPS-derived attitude signals in flight control computers. IC Role / Device Role / Timing Role: Dual SPST analog switch routing conditioned sensor outputs to ADC input channels with sub-microsecond settling. Use Value: Flat 30 Ω rDS(on) ensures identical gain scaling across both signal paths, eliminating calibration drift during mode transitions. |
Use Scenario: Switching between forward-looking infrared (FLIR) and electro-optical (EO) camera feeds in tactical UAV video downlink. IC Role / Device Role / Timing Role: High-isolation analog switch enabling seamless video source selection without ghosting or crosstalk on 75 Ω coaxial lines. Use Value: >50 dB off-isolation at 1 MHz preserves NTSC luminance/chrominance separation and prevents composite video degradation. |
| Audio Signal Conditioning | Sample/Hold Circuits |
Use Scenario: Multiplexing microphone preamplifier outputs in secure voice communication transceivers operating in jet cockpit environments. IC Role / Device Role / Timing Role: Low-leakage (<2 nA) analog switch selecting active channel before anti-aliasing filtering and digitization. Use Value: Ultra-low ID(on) prevents DC offset accumulation in high-gain mic amps, maintaining SNR >90 dB over temperature. |
Use Scenario: Holding sampled radar return pulses during analog-to-digital conversion in pulse-Doppler receiver chains. IC Role / Device Role / Timing Role: Precision switch isolating hold capacitor from input source during acquisition phase with minimal charge injection. Use Value: <1 pC charge injection limits aperture error to <0.01% FS, preserving dynamic range in 14-bit IF sampling stages. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual SPST analog switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DG181AA/883 | Same die, 10-pin metal can package; lower thermal dissipation (450 mW vs. 825 mW); –25 °C to +85 °C temp range | Limited to ground-based or non-extreme thermal environments; unsuitable for engine-mounted or space-qualified use | Select DG181AA/883 only when cost and board space constrain requirements and extended temperature is not needed. |
| ADG1212BRUZ | CMOS process; 120 Ω rDS(on); 0.01 pC charge injection; –40 °C to +125 °C; no radiation hardening | Higher on-resistance increases gain error in precision video; lacks TID/SEL qualification for mission-critical platforms | Use ADG1212BRUZ only in commercial-grade industrial controls where radiation tolerance is unnecessary and layout allows higher rDS(on). |
Compared with DG181AP, DG181AA/883 trades thermal robustness and extended temperature for smaller footprint, while ADG1212BRUZ offers lower charge injection but sacrifices radiation hardness, analog linearity, and military reliability certification required in aerospace deployments.
Availability
DG181AP is available at Aetrix Electronics and suitable for guidance and control systems, video signal routing in defense platforms, audio conditioning in secure comms, sample/hold circuits in radar receivers, and radiation-tolerant instrumentation requiring stable component supply across long production lifecycles.
Supply support for DG181AP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global semiconductor manufacturer specializing in discrete power MOSFETs, diodes, optoelectronics, and precision analog switches for high-reliability applications.
The DG181AP belongs to the DG180/181/182 family-designed specifically for radiation-hardened, low-distortion analog signal switching in aerospace, defense, and space electronics where parameter stability under extreme conditions is mandatory.
FAQ
What is the maximum allowable voltage difference between VL and VR on the DG181AP?
The DG181AP datasheet specifies a maximum voltage difference of 8 V between VL and VR. This limit ensures safe operation of the internal TTL-compatible logic driver and prevents breakdown in the substrate isolation structure. Exceeding this rating risks permanent damage to the logic interface circuitry and may compromise radiation hardness performance. Always maintain VL and VR within 8 V differential in all operating conditions for the DG181AP.
Does the DG181AP support bidirectional analog signal flow in both SPST channels?
Yes, the DG181AP supports fully bidirectional analog signal flow through both S1/D1 and S2/D2 switch pairs. Each JFET channel conducts equally well in either direction when ON, with matched rDS(on) and capacitance characteristics. This symmetry is essential for AC-coupled video and audio applications where signal polarity reversal must not affect performance. The DG181AP's bidirectional capability is explicitly confirmed in its functional description and switching test circuits.
What is the guaranteed minimum off-isolation (OIRR) for the DG181AP at 10 MHz?
The DG181AP guarantees off-isolation (OIRR) >50 dB at 1 MHz, but the datasheet does not specify a guaranteed minimum value at 10 MHz. Measured data shows OIRR >40 dB at 10 MHz under standard test conditions (RL = 75 Ω), though this is not production-tested or warranted. For 10 MHz–critical applications like high-speed data acquisition multiplexing, system-level validation of actual isolation is required. The DG181AP's rated performance remains defined at 1 MHz per specification.
Can the DG181AP operate with V+ = +12 V and V– = –12 V instead of the nominal ±15 V?
Yes, the DG181AP supports V+ to V– up to 36 V, so operation at ±12 V is fully within specification. Analog signal range adjusts proportionally: with ±12 V supplies, the guaranteed full-range is approximately –6 V to +12 V. All key parameters-including rDS(on), leakage, and switching times-remain valid at this reduced rail voltage. This flexibility allows integration into legacy 24 V aircraft power systems without derating, confirming the DG181AP's adaptability across military platform voltages.
Is the DG181AP pin-compatible with the DG180AP or DG182AP?
Yes, the DG181AP is pin-compatible with DG180AP and DG182AP-same 14-pin sidebraze package, identical pinout, and shared footprint. The only differences are rDS(on) (10 Ω / 30 Ω / 75 Ω) and corresponding leakage and bandwidth trade-offs. This allows direct substitution in existing layouts when adjusting for signal fidelity versus speed requirements. All three share identical mechanical mounting, thermal interface, and PCB land pattern for the DG181AP and its siblings.
DG181AP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- SPST - NC
- Multiplexer/Demultiplexer Circuit:
- 1:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 30Ohm
- Channel-to-Channel Matching (ΔRon):
- -
- Voltage - Supply, Single (V+):
- -
- Voltage - Supply, Dual (V±):
- ±15V
- Switch Time (Ton, Toff) (Max):
- 150ns, 130ns
- -3db Bandwidth:
- -
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 9pF, 6pF
- Current - Leakage (IS(off)) (Max):
- 1nA
- Crosstalk:
- -
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 14-DIP
DG181AP FAQ
1.How can I place an order for DG181AP through Aetrix?
Please submit a Request for Quotation (RFQ) for DG181AP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG181AP reliable?
The price and inventory of DG181AP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG181AP is usually 5 days.
3.What payment methods are accepted for DG181AP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG181AP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG181AP?
DG181AP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG181AP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG181AP?
For technical support, including DG181AP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG181AP requirements.
6.How does Aetrix verify that DG181AP is sourced from the original manufacturer or authorized distributors?
All DG181AP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG181AP meets industry standards.
7.What is the process for return or replacement of DG181AP?
All DG181AP units undergo pre-shipment inspection (PSI). If there is an issue with DG181AP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG181AP part is unused and in its original packaging.
Return procedure for DG181AP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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