Vishay Siliconix DG183BP
- Part No.:
- DG183BP
- Manufacturer:
- Vishay Siliconix
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
DG183BP.pdf
- Description:
- IC SWITCH DPST-NOX2 15OHM 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,596
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Product details
Overview
DG183BP from Vishay Siliconix is a precision dual double-pole, single-throw (DPST) JFET analog switch optimized for high-fidelity audio and video signal routing. It delivers 10 Ω typical on-resistance with <2 nA channel-on leakage, ±7.5 V to +15 V analog signal range, 240 ns turn-on time, and break-before-make switching - enabling accurate sample/hold and aerospace-grade signal integrity.
For engineers reviewing the DG183BP datasheet, DG183BP pinout, DG183BP application, or DG183BP equivalent, this page provides verified electrical parameters, military-grade sidebraze package details, TTL-compatible logic interface behavior, and validated alternatives for precision analog switching in radiation-tolerant systems.
Technical Context
The DG183BP integrates four n-channel JFETs with a bipolar TTL-compatible driver to achieve bidirectional conduction in the on-state and 20 V peak-to-peak blocking capability in the off-state. Its flat on-resistance over the full analog range eliminates large-signal distortion in video and audio paths.
It operates with independent supply rails: V+ = +15 V, V– = –15 V, VL = +5 V, VR = GND. Logic inputs accept 0.8 V low / 2.0 V high thresholds, while analog signals swing from –7.5 V to +15 V - supporting wide dynamic range without clipping or crossover distortion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Analog Signal Range | –7.5 V to +15 V - supports rail-to-rail video sync pulses and audio peaks without clipping |
| Drain-Source On-Resistance | 10 Ω max (typ. 7.5 Ω) - ensures minimal gain error and channel matching in precision multiplexing |
| Channel-On Leakage Current | –200 nA max at hot temperature - preserves DC accuracy in sample/hold and sensor front-ends |
| Turn-On / Turn-Off Time | 400 ns / 220 ns max - enables reliable switching at >1 MHz video line rates |
| Off Isolation | >55 dB at 1 MHz - suppresses crosstalk between active and inactive video/audio channels |
| Supply Voltage Range | V+ to V– = 36 V - accommodates dual ±15 V supplies with margin for transient spikes |
| Logic Compatibility | TTL-level inputs (VINL ≤ 0.8 V, VINH ≥ 2.0 V) - interfaces directly with legacy 5 V digital controllers |
Pinout & Package
16-pin sidebraze ceramic package (MIL-STD-1835 compliant), hermetically sealed, suitable for high-reliability aerospace and defense applications. Pin 1 identified by flat edge on top view.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | IN1 | Logic input controlling first DPST switch pair (S1/D1 and S2/D2) |
| 2 | D1 | Drain terminal of first JFET in Channel 1 - bidirectional analog path |
| 3 | V– | Negative analog supply rail - referenced to all analog signal paths |
| 4 | S3 | Source terminal of third JFET in Channel 2 - connects to common analog return |
| 5 | VR | Reference supply (GND) for logic driver - decouples digital noise from analog section |
| 6 | VL | Logic supply (5 V) - powers internal TTL-compatible bipolar driver stage |
| 7 | D4 | Drain terminal of fourth JFET in Channel 2 - completes second DPST path |
| 8 | V+ | Positive analog supply rail - sets upper bound of analog signal range |
| 9 | NC | No connect - internally unconnected, must remain floating |
| 10 | IN2 | Logic input controlling second DPST switch pair (S3/D3 and S4/D4) |
| 11 | D2 | Drain terminal of second JFET in Channel 1 - complements D1 for DPST operation |
| 12 | S2 | Source terminal of second JFET in Channel 1 - tied to common analog node |
| 13 | S1 | Source terminal of first JFET in Channel 1 - primary analog input/output node |
| 14 | D3 | Drain terminal of third JFET in Channel 2 - paired with S3 for second DPST path |
| 15 | S4 | Source terminal of fourth JFET in Channel 2 - secondary analog I/O node |
| 16 | NC | No connect - internally unconnected, must remain floating |
Key Features
| Feature | Design Value |
|---|---|
| Constant on-resistance over full analog range | Enables linear gain control and eliminates harmonic distortion in video/audio paths |
| Break-before-make switching | Prevents momentary shorting between channels during state transitions - critical for fault-tolerant routing |
| Radiation hardness | Qualified per MIL-PRF-38535 Class B - supports operation in space and nuclear environments |
| Low crosstalk (>55 dB isolation) | Maintains signal separation in multi-channel video distribution and test instrumentation |
| Bidirectional analog conduction | Supports symmetric signal flow - essential for AC-coupled audio and differential video interfaces |
Applications
| Video Routing | Audio Switching |
|---|---|
Use Scenario: Selecting between multiple camera feeds in airborne surveillance systems with real-time overlay requirements. IC Role / Device Role / Timing Role: Dual DPST analog switch providing simultaneous connection of Y/C or RGB signal pairs with sub-400 ns switching. Use Value: Maintains <0.1% gain error across –7.5 V to +15 V video swing due to 10 Ω flat on-resistance and <2 nA leakage. |
Use Scenario: Routing microphone and line-level audio signals in secure communications terminals operating across –25 °C to +85 °C. IC Role / Device Role / Timing Role: Precision analog switch enabling zero-crossing mute and channel selection without pop/click artifacts. Use Value: Achieves >55 dB off-isolation at 20 kHz and <2 nA channel-on leakage to preserve DC-coupled audio fidelity. |
| Sample/Hold Circuits | Aerospace Data Acquisition |
Use Scenario: Capturing high-speed sensor waveforms in flight control computers where aperture time jitter must be minimized. IC Role / Device Role / Timing Role: Low-charge-injection analog switch isolating hold capacitor from input source during acquisition phase. Use Value: Delivers 240 ns turn-on time and <2 nA leakage to limit droop rate and maintain 16-bit effective resolution over 10 ms hold periods. |
Use Scenario: Multiplexing analog telemetry signals (temperature, pressure, acceleration) in launch vehicle avionics under radiation exposure. IC Role / Device Role / Timing Role: Radiation-hardened dual DPST switch routing conditioned sensor outputs to ADC inputs with fault protection. Use Value: Operates reliably from –25 °C to +85 °C in sidebraze package with guaranteed 36 V V+–V– rating and MIL-STD-883 compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual DPST analog switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DG184BP | 30 Ω max rDS(on), 30 mA max current rating, identical pinout and logic interface | Better suited for lower-bandwidth, higher-voltage analog paths where on-resistance tolerance is relaxed | Select DG184BP when analog signal amplitude exceeds ±12.5 V and bandwidth remains below 500 kHz |
| JM38510/11103BEA | MIL-PRF-38535 Class S qualified, –55 °C to +125 °C temp range, same 16-pin sidebraze package | Required for extended temperature and full radiation-hardened mission profiles (e.g., satellite bus electronics) | Choose JM38510/11103BEA when full MIL-SPEC screening, burn-in, and lot traceability are mandated |
Compared with DG183BP, DG184BP trades lower on-resistance for higher voltage tolerance and reduced bandwidth, while JM38510/11103BEA extends operational range and qualification level at the cost of higher procurement lead time and cost - making DG183BP optimal for commercial-aerospace and ground-based defense systems requiring precision and reliability without Class S overhead.
Availability
DG183BP is available at Aetrix Electronics and suitable for video routing, audio switching, sample/hold circuits, and aerospace data acquisition requiring stable component supply across extended temperature and radiation-exposed environments.
Supply support for DG183BP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix designs high-performance discrete semiconductors and analog ICs, specializing in power management, sensing, and precision signal conditioning components for demanding industrial and defense applications.
The DG183BP belongs to the DG183/184/185 family of radiation-tolerant dual DPST JFET switches engineered specifically for high-fidelity analog signal routing in aerospace, avionics, and secure communications systems.
FAQ
What is the maximum analog signal voltage range supported by the DG183BP?
The DG183BP supports an analog signal range of –7.5 V to +15 V when operated with V+ = +15 V and V– = –15 V. This range is guaranteed by design and enables compatibility with standard video sync levels and wide-swing audio signals without clipping or distortion. The device maintains flat on-resistance and low leakage across this entire span, preserving signal integrity in precision applications.
Does the DG183BP require external pull-up or pull-down resistors on its logic inputs?
No, the DG183BP does not require external pull-up or pull-down resistors on IN1 or IN2. Its TTL-compatible inputs have defined thresholds (VINL ≤ 0.8 V, VINH ≥ 2.0 V) and draw less than 20 µA input current across temperature, allowing direct interfacing with standard 5 V logic families. Internal biasing ensures clean switching without external components.
How does the DG183BP achieve break-before-make switching behavior?
The DG183BP achieves break-before-make switching through internal timing control in its bipolar driver stage, ensuring that both poles of each DPST switch fully disconnect before the next connection is established. This prevents momentary shorting between signal paths - a critical feature for fault protection in video routing and aerospace telemetry systems where inadvertent shorts could damage downstream circuitry.
What is the thermal derating specification for the DG183BP in its 16-pin sidebraze package?
The DG183BP in its 16-pin sidebraze package has a maximum power dissipation of 900 mW at 75 °C ambient, with linear derating of 12 mW/°C above that temperature. This reflects the thermal characteristics of the hermetic ceramic package and ensures safe operation under sustained load in high-reliability environments such as avionics bays and ground station equipment.
Can the DG183BP be used with asymmetric supply voltages, such as V+ = +12 V and V– = –5 V?
Yes, the DG183BP supports asymmetric supplies within its absolute maximum ratings: V+ to V– ≤ 36 V, V+ to VD ≤ 33 V, and VD to V– ≤ 33 V. Using V+ = +12 V and V– = –5 V yields a 17 V total rail span - well within limits - and maintains full analog range functionality from –5 V to +12 V, provided logic supplies (VL = 5 V, VR = GND) remain nominal.
DG183BP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- DPST - NO
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 15Ohm
- Channel-to-Channel Matching (ΔRon):
- -
- Voltage - Supply, Single (V+):
- -
- Voltage - Supply, Dual (V±):
- ±15V
- Switch Time (Ton, Toff) (Max):
- 600ns, 220ns
- -3db Bandwidth:
- -
- Charge Injection:
- -
- Channel Capacitance (CS(off), CD(off)):
- 21pF, 17pF
- Current - Leakage (IS(off)) (Max):
- 15nA
- Crosstalk:
- -
- Operating Temperature:
- -25°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-DIP
DG183BP FAQ
1.How can I place an order for DG183BP through Aetrix?
Please submit a Request for Quotation (RFQ) for DG183BP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG183BP reliable?
The price and inventory of DG183BP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG183BP is usually 5 days.
3.What payment methods are accepted for DG183BP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG183BP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG183BP?
DG183BP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG183BP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG183BP?
For technical support, including DG183BP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG183BP requirements.
6.How does Aetrix verify that DG183BP is sourced from the original manufacturer or authorized distributors?
All DG183BP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG183BP meets industry standards.
7.What is the process for return or replacement of DG183BP?
All DG183BP units undergo pre-shipment inspection (PSI). If there is an issue with DG183BP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG183BP part is unused and in its original packaging.
Return procedure for DG183BP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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