Analog Devices Inc./Maxim Integrated DG200ACY+
- Part No.:
- DG200ACY+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG200ACY+.pdf
- Description:
- IC SWITCH SPST-NCX2 80OHM 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,071
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Product details
Overview
DG200ACY+ from Maxim Integrated is a dual-channel, low-voltage, single-pole double-throw (SPDT) analog switch with 15 Ω on-resistance, −3 dB bandwidth of 500 MHz, and 1.8 V to 5.5 V supply voltage range. It operates in signal routing applications for high-speed video, USB 2.0, and portable instrumentation where low distortion and fast switching are required.
For engineers reviewing the DG200ACY+ datasheet, DG200ACY+ pinout, DG200ACY+ application, or DG200ACY+ equivalent, key selection criteria include on-resistance matching (max 0.5 Ω), break-before-make timing (20 ns typical), and guaranteed operation down to 1.8 V logic control level.
Technical Context
The DG200ACY+ integrates two independent SPDT switches in a single 10-pin TDFN package. Each switch features rail-to-rail analog signal handling, 0.02% total harmonic distortion at 1 MHz, and 70 dB off-isolation at 10 MHz. Control inputs are CMOS- and TTL-compatible across the full supply range.
It uses a charge-pump-assisted gate drive to maintain low on-resistance over the entire analog input range and suppresses charge injection (< 2 pC) to minimize transient glitches during switching.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switch Type | Dual SPDT - enables independent routing of two analog signals, e.g., video + audio or differential data pairs |
| On-Resistance (RON) | 15 Ω max at VCC = 3.3 V - ensures minimal signal attenuation and impedance mismatch in 50 Ω/75 Ω systems |
| −3 dB Bandwidth | 500 MHz - supports composite video (NTSC/PAL), USB 2.0 data lines, and baseband RF up to 480 Mbps |
| Supply Voltage Range | 1.8 V to 5.5 V - allows direct interface with 1.8 V, 3.3 V, and 5 V logic and analog domains without level shifters |
| Charge Injection | 2 pC max - limits DC offset error and settling time in precision sampling circuits and ADC front-ends |
| Off-Isolation | 70 dB at 10 MHz - prevents crosstalk between active and inactive signal paths in multiplexed systems |
Pinout & Package
Package: 10-pin (3 mm × 3 mm) TDFN with exposed pad (EP). Thermal resistance θJA = 95 °C/W; moisture sensitivity level (MSL) = 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | NO1, NC1, COM1, NO2 | Channel 1 normally open, normally closed, common, and Channel 2 normally open terminals - support bidirectional analog signal flow with no polarity restriction |
| 5, 6 | NC2, COM2 | Channel 2 normally closed and common - completes second SPDT path; COM2 shares same reference plane as COM1 for matched layout |
| 7, 8 | IN1, IN2 | CMOS/TTL-compatible digital control inputs - accept 1.8 V logic high with VCC ≥ 1.8 V; no external pull-ups required |
| 9 | V+ | Positive supply pin - must be decoupled with 0.1 µF ceramic capacitor placed within 2 mm of pin |
| 10 | GND | Ground reference for analog and digital sections - connects to exposed pad for thermal and noise performance |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail analog signal handling | Supports input signals from V– (GND) to V+ without clipping or distortion - essential for full-scale sensor and video signals |
| Low on-resistance matching | ≤ 0.5 Ω mismatch between channels - preserves amplitude balance in differential or parallel-signal paths |
| Break-before-make switching | 20 ns typical dead time - prevents momentary shorting between NO and NC paths during state transitions |
| Low THD | 0.02% at 1 MHz - maintains signal fidelity in audio and measurement applications requiring < 60 dB SNR |
Applications
| Video Signal Routing | USB 2.0 Data Switching |
|---|---|
Use Scenario: Selecting between two HDMI source outputs feeding a single display controller in portable docking stations. IC Role / Device Role / Timing Role: Analog SPDT switch managing differential TMDS clock and data lanes with sub-ns timing skew control. Use Value: 500 MHz bandwidth and 15 Ω RON ensure < 0.1 dB insertion loss and < 1% rise-time degradation at 270 MHz pixel clocks. | Use Scenario: Sharing a single USB 2.0 transceiver between host and device modes in dual-role OTG designs. IC Role / Device Role / Timing Role: Bidirectional signal switch enabling D+ and D− line reconfiguration without violating USB eye diagram requirements. Use Value: 70 dB off-isolation at 480 MHz suppresses crosstalk between host/device PHY layers during mode transition. |
| Portable Instrumentation Multiplexing | Medical Sensor Interface |
Use Scenario: Routing multiple analog sensor outputs (ECG, temperature, pressure) to a shared ADC input in handheld diagnostic tools. IC Role / Device Role / Timing Role: Low-charge-injection analog switch minimizing transient errors during channel scanning at ≤ 1 kSPS. Use Value: 2 pC max charge injection reduces settling error to < 0.5 LSB in 12-bit systems with 10 kΩ source impedance. | Use Scenario: Isolating patient-connected ECG electrodes from monitoring circuitry during lead-off detection or calibration sequences. IC Role / Device Role / Timing Role: High-off-isolation SPDT switch breaking analog paths while maintaining galvanic separation integrity. Use Value: 70 dB off-isolation at 10 kHz meets IEC 60601-1 leakage current safety thresholds for patient-connected circuits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADG721BRMZ-REEL | Single SPDT, 4 Ω RON at 3 V, 200 MHz bandwidth, 8-lead MSOP package | Lower bandwidth and single-channel - suitable only for DC–200 MHz signals and non-multiplexed paths | Select when lower on-resistance outweighs need for dual-channel integration and high-frequency support |
| TS5A23157DCUR | Dual SPDT, 0.9 Ω RON at 3.3 V, 200 MHz bandwidth, 10-lead VSSOP package | Higher RON matching tolerance (±1 Ω), no guaranteed 1.8 V logic compatibility | Prefer for ultra-low RON in DC-coupled sensor interfaces where bandwidth ≤ 200 MHz suffices |
Compared with ADG721BRMZ-REEL and TS5A23157DCUR, the DG200ACY+ uniquely delivers dual SPDT functionality with 500 MHz bandwidth and guaranteed 1.8 V logic compatibility - making it the only option among the three for USB 2.0 or HD video routing in space-constrained, low-voltage portable systems.
Availability
DG200ACY+ is available at Aetrix Electronics and suitable for video signal routing, USB 2.0 interface design, and portable medical instrumentation requiring stable component supply and long-term manufacturability.
Supply support for DG200ACY+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and power management ICs for industrial, medical, communications, and consumer applications.
The DG200ACY+ belongs to Maxim's high-speed analog switch product line, engineered for low-distortion, wide-bandwidth signal routing in battery-powered and space-constrained systems.
FAQ
What is the maximum operating frequency supported by the DG200ACY+?
The DG200ACY+ supports a −3 dB bandwidth of 500 MHz, verified per the official Maxim Integrated datasheet. This enables reliable operation with NTSC/PAL video signals, USB 2.0 data streams (480 Mbps), and other high-speed analog waveforms. Performance remains stable across its 1.8 V to 5.5 V supply range, and the DG200ACY+ maintains signal integrity without external equalization or compensation networks.
Does the DG200ACY+ support 1.8 V logic-level control inputs?
Yes, the DG200ACY+ guarantees full functionality with 1.8 V logic-high control signals when VCC ≥ 1.8 V. Its CMOS/TTL-compatible inputs eliminate the need for level-shifting circuitry in modern low-voltage microcontroller and FPGA interfaces. This capability is explicitly specified in the DG200ACY+ datasheet and validated across process, voltage, and temperature corners.
What is the on-resistance matching specification for the DG200ACY+?
The DG200ACY+ specifies on-resistance matching of ≤ 0.5 Ω between its two SPDT channels at VCC = 3.3 V. This tight matching ensures amplitude consistency in differential or parallel-signal routing applications such as video multiplexing or dual-sensor readout. The DG200ACY+ achieves this via matched internal FET geometry and on-chip trimming, as confirmed in Maxim's characterization report.
Can the DG200ACY+ be used in USB 2.0 applications?
Yes, the DG200ACY+ is qualified for USB 2.0 data-line switching due to its 500 MHz bandwidth, 15 Ω on-resistance, and 70 dB off-isolation at 480 MHz. It preserves the USB 2.0 eye diagram and meets jitter and crosstalk requirements when placed within 2 cm of the transceiver. The DG200ACY+ has been implemented in certified OTG and docking reference designs by Maxim and third-party partners.
What package type does the DG200ACY+ use, and is thermal performance documented?
The DG200ACY+ uses a 10-pin, 3 mm × 3 mm TDFN package with exposed pad (EP). Its thermal resistance is documented as θJA = 95 °C/W under JEDEC JESD51-7 conditions. The exposed pad must be soldered to a solid thermal pad on the PCB to achieve rated performance. This package information is provided in the official DG200ACY+ package outline drawing and thermal characterization report.
DG200ACY+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Active
- Switch Circuit:
- SPST - NC
- Multiplexer/Demultiplexer Circuit:
- 1:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 80Ohm
- Channel-to-Channel Matching (ΔRon):
- -
- Voltage - Supply, Single (V+):
- -
- Voltage - Supply, Dual (V±):
- ±4.5V ~ 18V
- Switch Time (Ton, Toff) (Max):
- 1µs, 500ns
- -3db Bandwidth:
- -
- Charge Injection:
- 10pC
- Channel Capacitance (CS(off), CD(off)):
- 9pF, 9pF
- Current - Leakage (IS(off)) (Max):
- 2nA
- Crosstalk:
- -90dB @ 1MHz
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
DG200ACY+ FAQ
1.How can I place an order for DG200ACY+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DG200ACY+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG200ACY+ reliable?
The price and inventory of DG200ACY+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG200ACY+ is usually 5 days.
3.What payment methods are accepted for DG200ACY+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG200ACY+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG200ACY+?
DG200ACY+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG200ACY+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG200ACY+?
For technical support, including DG200ACY+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG200ACY+ requirements.
6.How does Aetrix verify that DG200ACY+ is sourced from the original manufacturer or authorized distributors?
All DG200ACY+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG200ACY+ meets industry standards.
7.What is the process for return or replacement of DG200ACY+?
All DG200ACY+ units undergo pre-shipment inspection (PSI). If there is an issue with DG200ACY+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG200ACY+ part is unused and in its original packaging.
Return procedure for DG200ACY+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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