Renesas DG401DY-T
- Part No.:
- DG401DY-T
- Manufacturer:
- Renesas
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG401DY-T.pdf
- Description:
- IC SWITCH SPST-NOX2 45OHM 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,930
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DG401DY-T from Intersil is a dual single-pole single-throw (SPST) monolithic CMOS analog switch with TTL/CMOS-compatible digital inputs, 45 Ω max ON resistance, <150 ns turn-on time, and ±15 V analog signal range. It operates from ±5 V to ±17 V supplies and is used in sample-and-hold circuits, data acquisition systems, and audio switching where low charge injection and bidirectional signal integrity are critical.
For engineers reviewing the DG401DY-T datasheet, DG401DY-T pinout, DG401DY-T application, or DG401DY-T equivalent, key selection considerations include its dual SPST topology, SOIC-16 package, guaranteed rDS(ON) ≤ 55 Ω over temperature, sub-100 ns tOFF, and compatibility with battery-operated and high-reliability systems requiring low leakage (<5 nA OFF-state) and minimal signal distortion.
Technical Context
The DG401DY-T implements two independent bilateral analog switches using a high-voltage silicon-gate CMOS process with epitaxial isolation to prevent latch-up. Each switch supports bidirectional AC/DC signals and maintains low rDS(ON) variation across ±15 V analog input range.
It features TTL/CMOS-compatible logic inputs (VIH ≥ 2.4 V, VIL ≤ 0.8 V), operates from single +5 V to +34 V or split ±5 V to ±17 V supplies, and delivers <35 μW quiescent power consumption. Charge injection is limited to 60 pC typical, enabling precision sample-and-hold performance without external correction.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switch Type | Dual SPST - provides two independent, bidirectional analog paths with separate digital control inputs (IN1, IN2). |
| Max ON Resistance | 55 Ω at full temperature range - ensures minimal signal attenuation and gain error in precision signal routing. |
| Turn-On/Off Time | tON ≤ 150 ns, tOFF ≤ 100 ns - enables fast multiplexing in high-speed data acquisition and communication systems. |
| Analog Signal Range | ±15 V - supports rail-to-rail analog signals up to 30 VP-P, compatible with industrial and instrumentation front-ends. |
| Charge Injection | 60 pC typical - reduces hold-mode voltage step error in sample-and-hold circuits without requiring large hold capacitors. |
| OFF-State Leakage | ±5 nA max at full temperature - preserves accuracy in high-impedance sensor interfaces and long-integration applications. |
| Supply Voltage Range | Single: +5 V to +34 V; Split: ±5 V to ±17 V - allows flexible integration into mixed-supply systems including battery-powered designs. |
Pinout & Package
Package: 16-lead SOIC (M16.15), 7.5 mm × 10.3 mm body, 1.27 mm pitch, RoHS-compliant Pb-free plus anneal finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (S1) | Source 1 | Analog input/output terminal for first SPST switch; bidirectional, matched to D1 for low THD. |
| 2 (IN1) | Digital Control Input 1 | TTL/CMOS-compatible enable for S1–D1 path; logic high closes switch, low opens it. |
| 3 (D1) | Drain 1 | Analog input/output terminal paired with S1; symmetric conduction supports AC coupling. |
| 4 (V+) | Positive Supply Rail | Connects to positive analog supply (up to +34 V); powers internal switch driver and level shifter. |
| 5 (GND) | Ground Reference | Logic and substrate reference; must be tied to system ground even in split-supply configurations. |
| 6 (V-) | Negative Supply Rail | Connects to negative analog supply (down to −17 V); defines lower bound of analog signal range. |
| 7 (VL) | Logic Supply Voltage | Independent 5 V logic rail; decouples digital switching noise from analog path and enables mixed-voltage control. |
| 8 (IN2) | Digital Control Input 2 | Independent TTL/CMOS enable for second SPST switch (S2–D2); supports asynchronous channel control. |
| 9 (S2) | Source 2 | Analog terminal for second SPST switch; electrically isolated from S1 but shares same supply domains. |
| 10 (D2) | Drain 2 | Paired analog terminal for S2; identical rDS(ON) matching and charge injection as D1/S1 pair. |
| 11–16 (NC) | No Connection | Unbonded pins; must remain unconnected per datasheet - no routing or grounding allowed. |
Key Features
| Feature | Design Value |
|---|---|
| Bilateral analog conduction | Enables true AC-coupled signal routing without polarity constraints - critical for audio and sensor front-ends. |
| Low charge injection (60 pC typ) | Minimizes hold-step error in sample-and-hold circuits, reducing need for trimming or active correction. |
| Split- or single-supply operation | Supports both ±15 V instrumentation rails and +12 V embedded systems - simplifies BOM consolidation. |
| Latch-up immunity | Epitaxial layer prevents destructive latch-up under transient overvoltage - enhances reliability in harsh environments. |
| Pb-free plus anneal packaging | RoHS-compliant 100% matte tin termination compatible with SnPb and Pb-free reflow profiles per J-STD-020. |
Applications
| Audio Switching | Data Acquisition |
|---|---|
|
Use Scenario: Routing line-level stereo signals between multiple sources (e.g., microphone, DAC, codec) in portable audio equipment. IC Role / Device Role / Timing Role: Dual SPST switch providing channel-selectable signal path with <−90 dB crosstalk and <72 dB OFF isolation. Use Value: Preserves wide dynamic range and low THD due to 45 Ω rDS(ON) matching and <12 pF OFF capacitance per channel. |
Use Scenario: Multiplexing sensor outputs (thermocouple, strain gauge) into a shared ADC in industrial PLC modules. IC Role / Device Role / Timing Role: Precision analog switch enabling sequential sampling with <60 pC charge injection and <5 nA leakage at 85°C. Use Value: Eliminates hold capacitor drift errors and maintains >16-bit effective resolution across temperature. |
| Sample and Hold Circuits | Battery-Operated Systems |
|
Use Scenario: Capturing fast transient waveforms in handheld oscilloscopes or power quality analyzers. IC Role / Device Role / Timing Role: Low-jitter, low-charge-injection switch controlling hold capacitor connection during acquisition phase. Use Value: Achieves <150 ns aperture time with sub-1 mV droop over 10 ms hold period using 10 nF capacitor. |
Use Scenario: Power management in medical wearables, enabling selective activation of sensor subsystems to extend battery life. IC Role / Device Role / Timing Role: Ultra-low-power analog switch (<35 μW) isolating unused analog paths while maintaining signal integrity. Use Value: Reduces system standby current by >90% versus discrete FET solutions, extending runtime by 3× in 3.7 V Li-ion systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual SPST analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HI-5041 | Identical pinout and SPST functionality; 35 Ω max rDS(ON) at +25°C, but 75 Ω max over full −40°C to +85°C range. | Higher ON resistance variation limits use in precision DC-coupled systems requiring <0.01% gain stability. | Select HI-5041 only when cost sensitivity outweighs tight rDS(ON) matching requirements. |
| ADG1412 | 4-channel SPST, 1.8 Ω max rDS(ON), but requires 2.7–5.5 V logic supply and lacks ±17 V analog capability. | Not suitable for ±15 V signal routing; optimized for low-voltage, high-precision instrumentation, not wide-range industrial inputs. | Choose ADG1412 for battery-powered 3.3 V systems needing ultra-low ON resistance, not for legacy ±15 V infrastructure. |
Compared with HI-5041 and ADG1412, DG401DY-T uniquely balances wide analog voltage range (±17 V), robust temperature-stable rDS(ON), and industry-standard SOIC-16 footprint - making it optimal for retrofitting legacy test equipment and industrial controllers where supply flexibility and reliability are prioritized over ultra-low resistance.
Availability
DG401DY-T is available at Aetrix Electronics and suitable for audio switching, data acquisition, and sample-and-hold applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.
Supply support for DG401DY-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) is a U.S.-based semiconductor designer specializing in high-performance analog and power management ICs for industrial, aerospace, and communications markets.
The DG401DY-T belongs to Intersil's monolithic CMOS analog switch family, engineered for precision signal routing in high-reliability systems where low charge injection, latch-up immunity, and wide supply tolerance are mandatory design requirements.
FAQ
What is the maximum analog signal voltage supported by the DG401DY-T?
The DG401DY-T supports analog signals up to ±15 V, corresponding to a 30 VP-P range. This is enabled by its 44 V maximum V+ to V− rating and internal protection architecture. Operation beyond ±15 V risks exceeding absolute maximum ratings and may cause irreversible damage to the DG401DY-T. Always maintain analog inputs within the specified supply rails.
Does the DG401DY-T require a separate logic supply voltage?
Yes, the DG401DY-T requires VL = 5 V for its digital interface, independent of analog supply rails (V+, V−). This separation prevents digital switching noise from coupling into analog paths. The DG401DY-T will not function correctly if VL is omitted or mismatched - the logic inputs (IN1, IN2) are referenced to VL, not GND or V+.
Can the DG401DY-T be used with single-supply operation?
Yes, the DG401DY-T supports single-supply operation from +5 V to +34 V. In this mode, V− must be connected to GND, V+ to the positive rail, and analog signals referenced accordingly. The DG401DY-T maintains full rDS(ON) performance and switching speed under single-supply conditions, as verified in the datasheet's electrical specifications table.
What is the thermal resistance (θJA) of the DG401DY-T in its SOIC package?
The DG401DY-T in 16-lead SOIC (M16.15) has a typical junction-to-ambient thermal resistance (θJA) of 115°C/W when mounted on a high-thermal-conductivity test board in free air. This value assumes standard JEDEC PCB layout; actual θJA in end-equipment depends on copper area, airflow, and adjacent heat sources. Exceeding 150°C junction temperature will permanently damage the DG401DY-T.
Is the DG401DY-T pin-compatible with other devices in the DG401/DG403 family?
Yes, the DG401DY-T shares identical pinout with all DG401 variants (e.g., DG401DYZ, DG401DVZ) and maintains mechanical and electrical compatibility with the DG403 series for layout reuse. However, DG403 is dual SPDT - swapping DG401DY-T for DG403DY-T requires logic redesign due to differing truth tables and terminal assignments, even though physical mounting is identical.
DG401DY-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Switch Circuit:
- SPST - NO
- Multiplexer/Demultiplexer Circuit:
- 1:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 45Ohm
- Channel-to-Channel Matching (ΔRon):
- 3Ohm
- Voltage - Supply, Single (V+):
- 5V ~ 34V
- Voltage - Supply, Dual (V±):
- ±5V ~ 17V
- Switch Time (Ton, Toff) (Max):
- 150ns, 100ns
- -3db Bandwidth:
- -
- Charge Injection:
- 60pC
- Channel Capacitance (CS(off), CD(off)):
- 12pF, 12pF
- Current - Leakage (IS(off)) (Max):
- 500pA
- Crosstalk:
- -90dB @ 1MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DG401DY-T FAQ
1.How can I place an order for DG401DY-T through Aetrix?
Please submit a Request for Quotation (RFQ) for DG401DY-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG401DY-T reliable?
The price and inventory of DG401DY-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG401DY-T is usually 5 days.
3.What payment methods are accepted for DG401DY-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG401DY-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG401DY-T?
DG401DY-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG401DY-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG401DY-T?
For technical support, including DG401DY-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG401DY-T requirements.
6.How does Aetrix verify that DG401DY-T is sourced from the original manufacturer or authorized distributors?
All DG401DY-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG401DY-T meets industry standards.
7.What is the process for return or replacement of DG401DY-T?
All DG401DY-T units undergo pre-shipment inspection (PSI). If there is an issue with DG401DY-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG401DY-T part is unused and in its original packaging.
Return procedure for DG401DY-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DG401DY-T Tags

-
SN74LVC1G3157DBVR
Texas Instruments
-
SN74LVC1G66DBVR
Texas Instruments
-
SN74LVC1G66DCKR
Texas Instruments

-
SN74LVC1G3157DSFR
Texas Instruments

-
1P1G3157QDCKRQ1
Texas Instruments

-
SN74LVC2G66DCUR
Texas Instruments
-
SN74LV4052APWR
Texas Instruments

-
74HC4051D,653
Nexperia USA Inc.
-
SN74LV4051APWR
Texas Instruments
-
CD74HC4052PWR
Texas Instruments
-
CD74HC4051PWR
Texas Instruments
-
TS5A3166DBVR
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

