Renesas DG403DVZ
- Part No.:
- DG403DVZ
- Manufacturer:
- Renesas
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DG403DVZ.pdf
- Description:
- IC SWITCH SPDT X 2 45OHM 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DG403DVZ from Intersil is a dual SPDT monolithic CMOS analog switch with TTL/CMOS-compatible digital inputs, 45 Ω max ON resistance, 150 ns max tON, and ±15 V analog signal range. It operates from split supplies (±5 V to ±17 V) or single +5 V to +34 V, and is used in sample-and-hold circuits, data acquisition systems, and audio switching where low charge injection (<60 pC) and high OFF isolation (72 dB) are critical.
For engineers reviewing the DG403DVZ datasheet, DG403DVZ pinout, DG403DVZ application, or DG403DVZ equivalent, this page delivers verified electrical specs, TSSOP-16 package details, dual SPDT functional behavior, break-before-make timing (5–12 ns), and RoHS-compliant Pb-free construction per M16.173 drawing.
Technical Context
The DG403DVZ implements two independent SPDT switches using a high-voltage silicon-gate CMOS process, enabling 44 V max V+− rating and latch-up immunity via epitaxial isolation. Its bilateral analog path supports bidirectional AC/DC signals with matched rDS(ON) (≤5 Ω channel-to-channel variation) and low temperature drift.
Control logic accepts TTL/CMOS levels (VIL ≤ 0.8 V, VIH ≥ 2.4 V) and drives internal transmission gates with <1 μA input current. The VL pin allows independent logic supply (up to V+ + 0.3 V), decoupling digital interface voltage from analog rail constraints.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switch Type | Dual SPDT - provides two independent single-pole double-throw analog paths for signal routing or multiplexing |
| Max ON Resistance | 45 Ω at ±15 V supplies - ensures minimal signal attenuation and gain error in precision DC/low-frequency paths |
| Turn-On Time (tON) | 150 ns max (RL = 300 Ω, CL = 35 pF) - supports sampling rates up to ~3 MHz in data acquisition front-ends |
| Charge Injection | 60 pC max - reduces pedestal error in sample-and-hold applications without requiring large hold capacitors |
| Analog Signal Range | ±15 V - accommodates industrial sensor outputs and audio line-level signals without clipping |
| Supply Voltage Range | Single: +5 V to +34 V; Split: ±5 V to ±17 V - enables operation across battery-powered and industrial rails |
| OFF Isolation | 72 dB at 1 MHz - suppresses crosstalk between active and inactive channels in multi-channel systems |
Pinout & Package
DG403DVZ is housed in a 16-lead Thin Shrink Small Outline Plastic Package (TSSOP), JEDEC MO-153-AB compliant, with 0.65 mm pitch, 4.3–4.5 mm body width (E1), and 4.9–5.1 mm length (D). Thermal resistance θJA = 150 °C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | Switch Inputs (S1–S4) | Analog source terminals - bidirectional, support ±15 V signals, connected internally to drain/source of MOSFET pairs |
| 5, 6, 7, 8 | Switch Outputs (D1–D4) | Analog drain terminals - routed to load or next stage; matched impedance and capacitance with S pins |
| 9, 10 | Digital Control Inputs (IN1, IN2) | TTL/CMOS-compatible logic inputs - drive both SPDT sections; low-level ≤0.8 V disables, high-level ≥2.4 V enables |
| 11 | GND | Analog/digital reference ground - common return for V−, V+, and logic; must be low-impedance |
| 12 | VL | Logic supply reference - sets input threshold; may be tied to V+, V−, or separate 5 V rail |
| 13, 14 | V−, V+ | Analog supply rails - define analog signal range; support split (±5 V to ±17 V) or single-ended operation |
| 15, 16 | No Connect (NC) | Unbonded die pads - no internal connection; must remain floating or grounded per layout best practice |
Key Features
| Feature | Design Value |
|---|---|
| Bilateral analog conduction | Enables identical performance for signal flow in either direction - essential for AC-coupled audio and bidirectional bus switching |
| Break-before-make switching | 5–12 ns guaranteed delay prevents momentary shorting between S1/S2 or S3/S4 paths during state transitions |
| Low OFF leakage | ±5 nA max over full temperature range - preserves voltage integrity on high-impedance nodes like integrator capacitors |
| Pb-free RoHS compliance | M16.173 TSSOP package with 100% matte tin termination - compatible with SnPb and Pb-free reflow profiles per J-STD-020 |
| High voltage tolerance | 44 V max V+− - permits control of 30 VP-P signals while maintaining safe margin against transients |
Applications
| Audio Switching | Data Acquisition |
|---|---|
|
Use Scenario: Routing line-level stereo signals between multiple sources (CD, DAC, mic preamp) in pro-audio mixers. IC Role / Device Role / Timing Role: Dual SPDT analog switch selecting between alternate input paths with sub-150 ns settling. Use Value: 72 dB OFF isolation prevents audible crosstalk; ±15 V range handles peak audio swings without clipping. |
Use Scenario: Multiplexing sensor outputs (thermocouple, strain gauge) into a shared ADC channel. IC Role / Device Role / Timing Role: Precision analog switch enabling sequential sampling with minimal charge injection-induced offset. Use Value: 60 pC max charge injection limits hold capacitor voltage error to <1 mV for 10 nF hold caps. |
| Sample and Hold Circuits | Automatic Test Equipment |
|
Use Scenario: Capturing fast transient waveforms in oscilloscope front-ends or power analyzer inputs. IC Role / Device Role / Timing Role: Low-rDS(ON) switch connecting signal to hold capacitor during acquisition phase. Use Value: 45 Ω max ON resistance minimizes time constant error with typical 1–10 nF hold capacitors. |
Use Scenario: Configuring stimulus/response paths in semiconductor ATE, routing DUT pins to SMUs or digitizers. IC Role / Device Role / Timing Role: High-isolation, low-leakage switch isolating test channels during calibration or safety interlocks. Use Value: ±5 nA max OFF leakage ensures stable bias conditions during long-duration parametric tests. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual SPDT analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4677EUP+ | 16-pin TSSOP, 4.5 Ω typical rDS(ON), 100 ns tON, but only ±5.5 V analog range and requires VL = V+ | Lower ON resistance suits low-voltage precision instrumentation; unsuitable for ±15 V industrial sensors | Select MAX4677EUP+ when system uses ≤±5.5 V analog rails and prioritizes speed over voltage range |
| ADG1434BRUZ | 16-pin TSSOP, 4.7 Ω rDS(ON), 170 ns tON, ±15 V range, but 1 μA max IIL vs DG403DVZ's 1 μA max (same spec), and higher 100 pC charge injection | Compatible voltage range and pinout; higher charge injection increases hold error in precision S&H | Select ADG1434BRUZ when layout reuse is critical and charge injection sensitivity is relaxed |
Compared with MAX4677EUP+ and ADG1434BRUZ, DG403DVZ uniquely balances ±15 V signal handling, 60 pC charge injection, and 45 Ω ON resistance in a RoHS-compliant TSSOP-making it optimal for industrial data acquisition where voltage range and hold accuracy are co-constrained.
Availability
DG403DVZ is available at Aetrix Electronics and suitable for data acquisition, sample-and-hold circuits, and audio switching requiring stable component supply across extended temperature (-40°C to +85°C) and high-reliability industrial environments.
Supply support for DG403DVZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) designs high-performance analog and mixed-signal ICs, with ISO9001-certified manufacturing and a focus on reliability in industrial, aerospace, and communications markets.
DG403DVZ belongs to Intersil's monolithic CMOS analog switch product line, engineered for precision signal routing in systems demanding low distortion, high isolation, and wide supply flexibility - especially where legacy compatibility and proven field reliability are required.
FAQ
What is the maximum analog signal voltage supported by DG403DVZ?
DG403DVZ supports analog signals from −15 V to +15 V relative to GND, as specified in the Electrical Specifications table under "Analog Signal Range, VANALOG". This ±15 V range is guaranteed over the full −40°C to +85°C operating temperature range and applies when V+ = +15 V and V− = −15 V. Exceeding these limits risks substrate diode conduction and increased leakage.
Does DG403DVZ require external pull-up resistors on its digital control inputs?
No, DG403DVZ does not require external pull-up resistors. Its digital inputs (IN1, IN2) draw less than 1 μA over full temperature and accept standard TTL/CMOS logic levels (VIL ≤ 0.8 V, VIH ≥ 2.4 V). The internal input structure is designed for direct connection to microcontroller GPIO or FPGA outputs without additional biasing components.
Can DG403DVZ operate from a single +12 V supply?
Yes, DG403DVZ supports single-supply operation from +5 V to +34 V. With V+ = +12 V and V− = GND (0 V), the analog signal range becomes 0 V to +12 V. The device maintains its 45 Ω max rDS(ON) and 150 ns max tON under these conditions, as confirmed in the Electrical Specifications table and Figure 14 of the datasheet.
What is the thermal resistance (θJA) of the DG403DVZ TSSOP package?
The DG403DVZ in its 16-lead TSSOP package (M16.173) has a typical junction-to-ambient thermal resistance (θJA) of 150 °C/W, measured under JEDEC-standard high-efficiency thermal test board conditions. This value assumes free-air convection and is used to estimate junction temperature rise under steady-state power dissipation.
Is DG403DVZ pin-compatible with DG403DY or DG403DYZ?
Yes, DG403DVZ is pin-compatible with DG403DY and DG403DYZ. All three share identical 16-lead pinouts (per datasheet Figure "DG403 TOP VIEW"), same functional block diagram, and identical absolute maximum ratings. The only differences are package type (TSSOP vs SOIC) and RoHS compliance (DG403DVZ and DG403DYZ are Pb-free; DG403DY is standard leaded).
DG403DVZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Active
- Switch Circuit:
- SPDT
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 45Ohm
- Channel-to-Channel Matching (ΔRon):
- 3Ohm
- Voltage - Supply, Single (V+):
- 5V ~ 34V
- Voltage - Supply, Dual (V±):
- ±5V ~ 17V
- Switch Time (Ton, Toff) (Max):
- 150ns, 100ns
- -3db Bandwidth:
- -
- Charge Injection:
- 60pC
- Channel Capacitance (CS(off), CD(off)):
- 12pF, 12pF
- Current - Leakage (IS(off)) (Max):
- 500pA
- Crosstalk:
- -90dB @ 1MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
DG403DVZ FAQ
1.How can I place an order for DG403DVZ through Aetrix?
Please submit a Request for Quotation (RFQ) for DG403DVZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG403DVZ reliable?
The price and inventory of DG403DVZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG403DVZ is usually 5 days.
3.What payment methods are accepted for DG403DVZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG403DVZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG403DVZ?
DG403DVZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG403DVZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG403DVZ?
For technical support, including DG403DVZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG403DVZ requirements.
6.How does Aetrix verify that DG403DVZ is sourced from the original manufacturer or authorized distributors?
All DG403DVZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG403DVZ meets industry standards.
7.What is the process for return or replacement of DG403DVZ?
All DG403DVZ units undergo pre-shipment inspection (PSI). If there is an issue with DG403DVZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG403DVZ part is unused and in its original packaging.
Return procedure for DG403DVZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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