Renesas DG403DVZ-T
- Part No.:
- DG403DVZ-T
- Manufacturer:
- Renesas
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DG403DVZ-T.pdf
- Description:
- IC SWITCH SPDT X 2 45OHM 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DG403DVZ-T from Intersil is a dual SPDT monolithic CMOS analog switch with TTL/CMOS-compatible digital inputs, 45Ω max ON resistance, 150ns max tON, and ±15V analog signal range. It operates from split supplies (±5V to ±17V) or single +5V to +34V, and is used in sample-and-hold circuits, data acquisition, and communication systems.
For engineers reviewing the DG403DVZ-T datasheet, DG403DVZ-T pinout, DG403DVZ-T application, or DG403DVZ-T equivalent, key selection criteria include break-before-make timing (5–12ns), low charge injection (60pC typ), high OFF isolation (72dB), and TSSOP-16 RoHS-compliant packaging for space-constrained industrial signal routing.
Technical Context
The DG403DVZ-T implements two independent SPDT switches using a high-voltage silicon-gate CMOS process with epitaxial layer latch-up protection. Its bilateral analog path supports bidirectional AC/DC signals across ±15V with minimal rDS(ON) variation.
Switch control uses active-high logic (IN1/IN2), enabling simultaneous channel selection with guaranteed break-before-make operation. Digital inputs accept TTL/CMOS levels (0.8V low / 2.4V high), and logic supply (VL) is independently configurable from 4.5V to V+.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switch Type | Dual SPDT - provides two independent single-pole double-throw analog paths for signal routing or multiplexing |
| Max ON Resistance | 45Ω at ±13.5V supplies - ensures minimal insertion loss and gain error in precision signal paths |
| Switching Time (tON/tOFF) | 150ns/100ns max - enables high-speed sampling in data acquisition and automatic test equipment |
| Charge Injection | 60pC typ - reduces voltage step errors in sample-and-hold and peak-detect applications |
| Analog Signal Range | ±15V - supports full-rail operation with ±15V op-amp interfaces and 30VP-P signal handling |
| Supply Voltage Range | Single: +5V to +34V; Split: ±5V to ±17V - accommodates legacy industrial rails and wide dynamic range systems |
| OFF Isolation | 72dB at 1MHz - prevents crosstalk between inactive channels in multi-channel instrumentation |
Pinout & Package
Package: 16-lead TSSOP (M16.173), Pb-free, RoHS compliant, 4.9mm × 6.5mm footprint, 1.2mm max height.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | S1, S2, S3, S4 | Source terminals - bidirectional analog inputs/outputs; S1/S2 pair controlled by IN1, S3/S4 by IN2 |
| 5, 6, 7, 8 | D1, D2, D3, D4 | Drain terminals - analog outputs/inputs; D1/D2 connect to S1/S2 when IN1 = HIGH; D3/D4 to S3/S4 when IN2 = HIGH |
| 9, 10 | IN1, IN2 | Digital control inputs - active-high TTL/CMOS logic; drive internal switch gates directly |
| 11 | GND | Analog/digital ground reference - common return for V-, VL, and signal paths |
| 12 | VL | Logic supply - powers internal level-shifting circuitry; must be ≥ GND −0.3V and ≤ V+ +0.3V |
| 13 | V+ | Positive analog supply - sets upper rail for analog signal range and switch bias |
| 14 | V− | Negative analog supply - sets lower rail; enables true bipolar operation down to −15V |
| 15, 16 | NC | No connection - internally unconnected; must remain floating per datasheet |
Key Features
| Feature | Design Value |
|---|---|
| Bilateral analog conduction | Enables identical performance for signal flow in either direction - critical for audio switching and transducer interfacing |
| Break-before-make timing | 5–12ns typical - prevents momentary shorting between D1/D2 or D3/D4 during state transitions |
| Low OFF capacitance | 12pF typ (CS(OFF)/CD(OFF)) - minimizes capacitive feedthrough and preserves high-frequency signal integrity |
| Latch-up immunity | Epitaxial layer process eliminates latch-up risk under transient overvoltage - enhances reliability in harsh environments |
| Pb-free TSSOP package | M16.173 footprint with 100% matte tin terminations - compatible with SnPb and Pb-free reflow profiles per J-STD-020 |
Applications
| Audio Switching | Data Acquisition |
|---|---|
Use Scenario: Routing line-level stereo signals between multiple sources and amplifiers in professional audio mixers. IC Role / Device Role / Timing Role: Dual SPDT analog switch providing isolated channel selection with <150ns settling for real-time mute/unmute. Use Value: 72dB OFF isolation prevents audible crosstalk; 45Ω ON resistance avoids level mismatch in 600Ω impedance-matched paths. |
Use Scenario: Multiplexing sensor inputs (thermocouples, strain gauges) into a shared ADC front-end in industrial PLC modules. IC Role / Device Role / Timing Role: Precision analog switch enabling sequential sampling with low charge injection (<60pC) to minimize hold capacitor voltage error. Use Value: ±15V analog range accommodates wide-output sensors; low leakage (<5nA) preserves accuracy over extended sample intervals. |
| Sample and Hold Circuits | Communication Systems |
Use Scenario: Capturing fast transient waveforms in oscilloscope front-ends where aperture uncertainty must be minimized. IC Role / Device Role / Timing Role: High-speed switch controlling hold capacitor charging path with precise break-before-make timing (5–12ns). Use Value: 150ns tON ensures sub-7MHz sampling rates; low rDS(ON) matching (≤5Ω) maintains channel-to-channel gain consistency. |
Use Scenario: Signal path switching in RF test set controllers, selecting between calibration standards and DUT interfaces. IC Role / Device Role / Timing Role: Analog routing element handling baseband I/Q signals up to 10MHz with minimal distortion. Use Value: −90dB crosstalk suppresses inter-channel interference; 39pF ON capacitance preserves bandwidth in 50Ω systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual SPDT analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4673ETE+ | Higher ON resistance (75Ω max), smaller TDFN-16 package (3mm × 3mm), 12-bit DAC integration not present in DG403DVZ-T | Targeted at portable medical devices requiring ultra-small footprint; lacks ±15V analog range support | Select MAX4673ETE+ only if board area is constrained and DAC functionality is needed; DG403DVZ-T preferred for industrial ±15V signal integrity |
| ADG1434YRUZ | Lower ON resistance (3.5Ω typ), higher supply voltage limit (±20V), but requires external level shifters for TTL input compatibility | Used in high-precision test equipment demanding sub-1Ω matching; incompatible with direct 5V logic drive without redesign | Choose ADG1434YRUZ when ultra-low rDS(ON) and matching are critical; DG403DVZ-T offers plug-and-play TTL/CMOS interface and proven robustness in Hi-Rel systems |
Compared with MAX4673ETE+ and ADG1434YRUZ, the DG403DVZ-T delivers optimal balance of speed (150ns), isolation (72dB), and ease-of-use (TTL/CMOS direct drive, ±15V range) for mid-performance industrial signal routing-without requiring layout changes or support ICs.
Availability
DG403DVZ-T is available at Aetrix Electronics and suitable for data acquisition, sample-and-hold circuits, and communication systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for DG403DVZ-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) is a U.S.-based semiconductor company specializing in high-performance analog and mixed-signal ICs for industrial, aerospace, and communications markets.
The DG403 series was designed specifically for precision analog signal routing in harsh environments, emphasizing latch-up immunity, wide supply flexibility, and low charge injection for measurement-critical applications.
FAQ
What is the maximum analog signal voltage the DG403DVZ-T can handle?
The DG403DVZ-T supports an analog signal range of ±15V, enabling it to pass 30VP-P signals without distortion. This is validated under full operating conditions (−40°C to +85°C) with V+ = +15V and V− = −15V. Exceeding ±15V risks forward-biasing internal substrate diodes, increasing leakage and potential damage.
Does the DG403DVZ-T require external level-shifting for TTL logic inputs?
No. The DG403DVZ-T has native TTL/CMOS-compatible digital inputs: logic "0" is defined as ≤0.8V and logic "1" as ≥2.4V, matching standard 5V TTL thresholds. No external level shifter is needed when driven directly from microcontrollers or logic families operating at 5V.
Can the DG403DVZ-T operate from a single +12V supply?
Yes. The DG403DVZ-T supports single-supply operation from +5V to +34V. With V+ = +12V and V− tied to GND, the analog signal range becomes 0V to +12V. Ensure VL is set to a valid logic supply (e.g., +5V) and that analog inputs remain within this 0V–12V window.
What is the thermal resistance (θJA) of the DG403DVZ-T in its TSSOP package?
The DG403DVZ-T in 16-lead TSSOP (M16.173) has a typical junction-to-ambient thermal resistance (θJA) of 150°C/W when mounted on a standard PCB in free air. This value assumes no copper pour or thermal vias; adding thermal relief significantly improves power dissipation capability.
Is the DG403DVZ-T pin-compatible with the SOIC-packaged DG403DY?
Yes. The DG403DVZ-T (TSSOP-16) shares identical pin numbering and function mapping with the DG403DY (SOIC-16), including NC pins at positions 15 and 16. Layout migration requires only footprint change-no netlist or schematic modification is needed.
DG403DVZ-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Switch Circuit:
- SPDT
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 45Ohm
- Channel-to-Channel Matching (ΔRon):
- 3Ohm
- Voltage - Supply, Single (V+):
- 5V ~ 34V
- Voltage - Supply, Dual (V±):
- ±5V ~ 17V
- Switch Time (Ton, Toff) (Max):
- 150ns, 100ns
- -3db Bandwidth:
- -
- Charge Injection:
- 60pC
- Channel Capacitance (CS(off), CD(off)):
- 12pF, 12pF
- Current - Leakage (IS(off)) (Max):
- 500pA
- Crosstalk:
- -90dB @ 1MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
DG403DVZ-T FAQ
1.How can I place an order for DG403DVZ-T through Aetrix?
Please submit a Request for Quotation (RFQ) for DG403DVZ-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG403DVZ-T reliable?
The price and inventory of DG403DVZ-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG403DVZ-T is usually 5 days.
3.What payment methods are accepted for DG403DVZ-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG403DVZ-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG403DVZ-T?
DG403DVZ-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG403DVZ-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG403DVZ-T?
For technical support, including DG403DVZ-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG403DVZ-T requirements.
6.How does Aetrix verify that DG403DVZ-T is sourced from the original manufacturer or authorized distributors?
All DG403DVZ-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG403DVZ-T meets industry standards.
7.What is the process for return or replacement of DG403DVZ-T?
All DG403DVZ-T units undergo pre-shipment inspection (PSI). If there is an issue with DG403DVZ-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG403DVZ-T part is unused and in its original packaging.
Return procedure for DG403DVZ-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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