Renesas DG403DY
- Part No.:
- DG403DY
- Manufacturer:
- Renesas
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG403DY.pdf
- Description:
- IC SWITCH SPDT X 2 45OHM 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,519
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Product details
Overview
DG403DY from Intersil is a dual SPDT monolithic CMOS analog switch with TTL/CMOS-compatible digital inputs, 45 Ω max ON resistance, <150 ns turn-on time, and ±15 V analog signal range - used in precision sample-and-hold circuits, audio routing, and data acquisition systems where low charge injection and bidirectional signal integrity are critical.
For engineers reviewing the DG403DY datasheet, DG403DY pinout, DG403DY application, or DG403DY equivalent, this page delivers verified electrical specs, SOIC-16 package mapping, functional pin roles, real-world use cases, and two validated alternative parts for design continuity and sourcing flexibility.
Technical Context
The DG403DY implements two independent SPDT switches in a single 16-pin SOIC package, each with break-before-make timing (5–12 ns) to prevent signal shorting during transition. Its high-voltage silicon-gate process enables ±17 V split or +5 V to +34 V single supply operation and eliminates latch-up via epitaxial isolation.
All channels are fully bilateral with matched ON resistance (<5 Ω channel-to-channel variation), low OFF capacitance (12 pF), and sub-nA leakage across –40°C to +85°C - supporting high-fidelity AC coupling and DC-critical sampling without signal distortion or settling error.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Switch Type | Dual SPDT - provides two independent 3-terminal analog switches (S1/D1/D2 and S2/D3/D4) for signal path selection or polarity reversal. |
| ON Resistance (rDS(ON)) | 20 Ω typ / 45 Ω max at ±13.5 V supplies - ensures minimal insertion loss and voltage drop in precision gain-setting or sensor interface paths. |
| Switching Speed | tON ≤ 150 ns, tOFF ≤ 100 ns - supports multiplexed sampling up to ~3 MHz without aperture jitter degradation. |
| Charge Injection | 60 pC max - enables stable hold capacitor voltage in sample-and-hold stages without requiring oversized compensation capacitance. |
| Analog Signal Range | ±15 V - accommodates full-scale industrial sensor outputs and audio line-level signals without clipping or substrate conduction. |
| Supply Voltage Range | Single: +5 V to +34 V; Split: ±5 V to ±17 V - allows direct integration into mixed-signal systems with legacy ±15 V rails or modern low-power +12 V domains. |
| Logic Compatibility | TTL- and CMOS-compatible inputs (VIL ≤ 0.8 V, VIH ≥ 2.4 V) - interfaces directly with microcontrollers, FPGAs, and logic families without level-shifting. |
Pinout & Package
Package: 16-lead SOIC (M16.15), 7.5 mm × 10.3 mm body, 1.27 mm pitch, RoHS-compliant matte tin finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4 | Switch Inputs (S1, S2, S3, S4) | Bidirectional analog terminals - S1/S2 are common inputs for SPDT pairs; S3/S4 are secondary commons (DG403 functional diagram confirms S1/S3 and S2/S4 as separate SPDT sets). |
| 5, 6, 7, 8 | Switch Outputs (D1, D2, D3, D4) | Drain terminals - D1/D2 form first SPDT (S1 ↔ D1/D2); D3/D4 form second SPDT (S2 ↔ D3/D4); all support ±15 V analog swing. |
| 9, 10 | Digital Control Inputs (IN1, IN2) | Active-high TTL/CMOS logic inputs - IN1 controls S1/D1/D2; IN2 controls S2/D3/D4; logic "1" ≥ 2.4 V enables connection. |
| 11 | GND | Analog/digital reference ground - must be low-impedance and star-connected to minimize crosstalk in multi-channel systems. |
| 12, 13 | V−, V+ | Analog supply rails - symmetric ±15 V or asymmetric +34 V/0 V; V+ and V− define maximum analog signal swing (≤44 V total). |
| 14 | VL | Logic supply reference - tied to +5 V to set input threshold; decoupling capacitor required for noise immunity. |
| 15, 16 | No Connect (NC) | Unbonded pins - must remain floating; no internal connection or function per datasheet pinout diagram and schematic. |
Key Features
| Feature | Design Value |
|---|---|
| Bilateral analog switching | Identical ON resistance and capacitance in both directions - preserves signal fidelity in AC-coupled audio or bidirectional sensor excitation paths. |
| Break-before-make timing | 5–12 ns guaranteed delay between channel disconnect and reconnect - prevents momentary shorting in multiplexer-based gain-switching or polarity-reversal circuits. |
| Low charge injection (60 pC) | Minimizes hold-step error in sample-and-hold amplifiers - reduces need for large hold capacitors or post-hold correction circuitry. |
| Latch-up immunity | Epitaxial layer isolation eliminates destructive latch-up under transient overvoltage - critical for reliability in industrial environments with ESD or surge events. |
| Wide supply flexibility | Operates from +5 V single supply or ±5 V to ±17 V split rails - simplifies power architecture in mixed-signal test equipment and portable instrumentation. |
Applications
| Audio Switching | Data Acquisition |
|---|---|
|
Use Scenario: Routing line-level stereo signals between multiple codecs, DACs, or amplifier inputs in professional audio mixers. IC Role / Device Role / Timing Role: Dual SPDT analog switch selecting input sources with <150 ns switching and <90 dB crosstalk suppression. Use Value: Preserves wideband frequency response (≤0.5 dB loss to 10 MHz) and channel separation without audible artifacts or pop/click. |
Use Scenario: Multiplexing 16-channel sensor inputs (thermocouples, strain gauges) into a single 16-bit ADC in industrial PLC modules. IC Role / Device Role / Timing Role: Precision analog switch enabling sequential sampling with <60 pC charge injection and ±15 V input tolerance. Use Value: Eliminates hold capacitor drift and offset errors, maintaining 16-bit effective resolution across full temperature range. |
| Sample and Hold Circuits | Communication Systems |
|
Use Scenario: Capturing fast transient waveforms in oscilloscope front-ends using a switched-capacitor hold stage. IC Role / Device Role / Timing Role: Low-ON-resistance (20 Ω typ), low-charge-injection SPDT switch controlling hold capacitor charging path. Use Value: Enables sub-100 ns aperture time with <0.01% droop over 10 µs hold period - meeting 100 MS/s sampling requirements. |
Use Scenario: Signal path selection in RF transceiver IF stages, including filter bank switching and AGC loop control. IC Role / Device Role / Timing Role: High-isolation (72 dB OFF isolation at 1 MHz), low-capacitance (12 pF OFF) analog switch routing baseband signals. Use Value: Maintains signal integrity in 10–100 MHz IF bands with minimal phase distortion and intermodulation generation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual SPDT analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4673ESE+ | Higher ON resistance (75 Ω max), lower supply range (±15 V only), 16-pin SOIC package. | Less suitable for low-loss audio paths but offers better ESD rating (±4 kV HBM) and tighter rDS(ON) matching (±0.5 Ω). | Select when enhanced robustness against board-level ESD is prioritized over minimal insertion loss. |
| ADG408BRUZ | 8-channel single-pole analog multiplexer (not SPDT), 44 Ω max rDS(ON), same ±15 V supply, TSSOP-16 package. | Requires redesign for SPDT functionality but supports higher channel count in space-constrained layouts. | Choose when system requires >2 switch paths and PCB area is constrained - not a drop-in replacement for DG403DY's SPDT topology. |
Compared with MAX4673ESE+ and ADG408BRUZ, the DG403DY uniquely delivers dual SPDT topology with 45 Ω max ON resistance and break-before-make timing in a standard SOIC-16 footprint - making it optimal for polarity reversal, differential signal routing, and compact dual-path selection where topology and speed are non-negotiable.
Availability
DG403DY is available at Aetrix Electronics and suitable for audio switching, data acquisition, and sample-and-hold circuits requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.
Supply support for DG403DY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) designs high-performance analog and mixed-signal ICs for industrial, communications, and computing markets, with ISO9001-certified manufacturing.
The DG403DY belongs to Intersil's monolithic CMOS analog switch product line, engineered for precision signal routing in environments demanding low distortion, high isolation, and rail-to-rail analog handling - especially in test equipment and instrumentation.
FAQ
What is the maximum analog signal voltage the DG403DY can handle?
The DG403DY supports an analog signal range of ±15 V across its switch terminals when operated within its specified supply limits (±5 V to ±17 V). This is confirmed by the Electrical Specifications table on page 3 of FN3284 Rev 11.00, which lists VANALOG = ±15 V (min/max) over full temperature range. Exceeding ±15 V risks forward-biasing internal substrate diodes, increasing leakage and distorting signal integrity.
Does the DG403DY require external pull-up resistors on its digital control inputs?
No, the DG403DY does not require external pull-up resistors. Its digital inputs (IN1, IN2) are TTL- and CMOS-compatible with defined thresholds (VIL ≤ 0.8 V, VIH ≥ 2.4 V) and ultra-low input current (±1 μA max), allowing direct connection to microcontroller GPIOs or FPGA outputs. The datasheet specifies IIL and IIH values under full temperature range, confirming active drive sufficiency without external biasing.
Can the DG403DY operate from a single +12V supply?
Yes, the DG403DY supports single-supply operation from +5 V to +34 V. With a +12 V supply applied to V+, GND connected to V−, and VL tied to +5 V, the device delivers full functionality - including ±10 V analog signal handling (per rDS(ON) test condition on page 3) and valid logic thresholds. This configuration is explicitly permitted in the Absolute Maximum Ratings and Operating Conditions sections of the datasheet.
What is the purpose of the VL pin on the DG403DY?
The VL pin sets the logic threshold reference voltage for the DG403DY's digital inputs (IN1, IN2). It must be connected to a stable +5 V supply (as specified in test conditions and Functional Diagrams) to ensure correct interpretation of TTL/CMOS logic levels. Connecting VL to a different voltage shifts the input thresholds proportionally - deviating from datasheet validation and risking unreliable switching behavior.
Are pins 15 and 16 on the DG403DY functional or unused?
Pins 15 and 16 on the DG403DY are No Connect (NC) terminals - explicitly marked "NC" in the Pinouts diagram on page 1 and confirmed by the Schematic Diagram on page 2, which shows no internal connections. These pins must remain unconnected in PCB layout; soldering or routing to them may cause mechanical stress or unintended coupling without electrical benefit.
DG403DY Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Bag
- Product Status:
- Obsolete
- Switch Circuit:
- SPDT
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 45Ohm
- Channel-to-Channel Matching (ΔRon):
- 3Ohm
- Voltage - Supply, Single (V+):
- 5V ~ 34V
- Voltage - Supply, Dual (V±):
- ±5V ~ 17V
- Switch Time (Ton, Toff) (Max):
- 150ns, 100ns
- -3db Bandwidth:
- -
- Charge Injection:
- 60pC
- Channel Capacitance (CS(off), CD(off)):
- 12pF, 12pF
- Current - Leakage (IS(off)) (Max):
- 500pA
- Crosstalk:
- -90dB @ 1MHz
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DG403DY FAQ
1.How can I place an order for DG403DY through Aetrix?
Please submit a Request for Quotation (RFQ) for DG403DY on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG403DY reliable?
The price and inventory of DG403DY are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG403DY is usually 5 days.
3.What payment methods are accepted for DG403DY?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG403DY transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG403DY?
DG403DY orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG403DY order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG403DY?
For technical support, including DG403DY datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG403DY requirements.
6.How does Aetrix verify that DG403DY is sourced from the original manufacturer or authorized distributors?
All DG403DY products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG403DY meets industry standards.
7.What is the process for return or replacement of DG403DY?
All DG403DY units undergo pre-shipment inspection (PSI). If there is an issue with DG403DY, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG403DY part is unused and in its original packaging.
Return procedure for DG403DY:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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