Analog Devices Inc./Maxim Integrated DG409CY

Overview

DG409CY from Maxim Integrated is a dual 4-channel CMOS analog multiplexer/demultiplexer designed for bidirectional signal routing in precision analog systems. It features guaranteed on-resistance matching ≤8Ω, on-resistance flatness ≤9Ω, low charge injection ≤15pC, and operates from ±5V to ±20V dual supplies or +5V to +30V single supply. It is used in data-acquisition systems requiring rail-to-rail signal handling and low channel-to-channel crosstalk.

For engineers reviewing the DG409CY datasheet, DG409CY pinout, DG409CY application, or DG409CY equivalent, key selection criteria include guaranteed channel matching, low leakage (<5nA at +85°C), TTL/CMOS-compatible digital control, ESD protection >2000V, and compatibility with test equipment and guidance systems demanding stable analog switching performance.

Technical Context

The DG409CY implements a dual independent 4:1 analog mux architecture with separate address inputs (A0, A1) and shared enable (EN) controlling two parallel switch banks (S1A–S4A/DA and S1B–S4B/DB). Each channel conducts bidirectionally with matched rDS(ON) across temperature and supply voltage.

Its internal CMOS decoder logic ensures break-before-make switching (tOPEN = 85–175ns), while rail-to-rail analog signal range (±10V typical at ±15V supplies) and low input off-leakage (<5nA at +85°C) support high-accuracy sampling in industrial and aerospace environments.

Key Specifications

Pinout & Package

Package: 16-pin Narrow SO (Small Outline), JEDEC MS-012AC, 3.9mm body width, 1.27mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar analog multiplexer applications.

Compared with ADG409BRZ and TS5A23157DGSR, the DG409CY uniquely delivers guaranteed 8Ω channel matching and 15pC charge injection within a 16-pin SO footprint compatible with legacy DG409 layouts-making it optimal for upgrading existing high-precision, wide-supply analog multiplexing designs.

Availability

DG409CY is available at Aetrix Electronics and suitable for data-acquisition systems, automated test equipment, and guidance and control systems requiring stable component supply, long-term obsolescence management, and traceable sourcing.

Supply support for DG409CY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for industrial, communications, and computing markets.

The DG409CY belongs to Maxim's high-reliability analog switch product line, engineered for precision signal routing in mission-critical instrumentation and control systems where channel matching, leakage, and ESD robustness are design-critical.

FAQ

What is the maximum allowable supply voltage difference for DG409CY?

The DG409CY specifies an absolute maximum voltage referenced to V−: V+ must not exceed V− + 44V. This allows operation with unbalanced supplies such as +24V and −5V (29V difference), provided the individual supply ratings (±5V to ±20V dual, or +5V to +30V single) are respected. Exceeding 44V differential risks permanent damage per the Absolute Maximum Ratings table.

Does DG409CY support single-supply operation, and how is it configured?

Yes, DG409CY supports single-supply operation from +5V to +30V. To configure: connect V− to GND, apply V+ to the positive rail, and ensure all analog signals remain within 0V to V+ (rail-to-rail). Digital inputs (A0, A1, EN) reference GND and accept standard TTL/CMOS logic levels. The analog signal range scales linearly with V+.

What is the guaranteed on-resistance flatness specification for DG409CY, and why does it matter?

DG409CY guarantees on-resistance flatness of ≤9Ω across its specified analog signal range. This means the variation in rDS(ON) from minimum to maximum measured at signal extremes (e.g., V− to V+) is bounded. It matters because flatness directly impacts gain linearity in amplifier or PGA circuits-critical in precision data acquisition where nonlinearity introduces harmonic distortion and measurement error.

How does the enable (EN) pin function in DG409CY, and what is its timing behavior?

The EN pin is an active-low enable: logic high disables both mux banks, placing all analog terminals in high-impedance state; logic low enables switching per address inputs. DG409CY guarantees tON(EN) ≤ 300ns and tOFF(EN) ≤ 600ns (dual-supply, +25°C), ensuring rapid channel activation/deactivation for time-critical sampling sequences in automated test systems.

Is DG409CY pin-compatible with the original industry-standard DG409?

Yes, DG409CY is explicitly documented as a pin-compatible plug-in upgrade for the industry-standard DG409. It shares identical pinout, package outline (16-pin Narrow SO), and functional logic (A0/A1 addressing, EN control, DA/DB outputs), allowing drop-in replacement without PCB modification while delivering improved channel matching, lower leakage, and enhanced ESD protection.