Renesas DG409DJZ
- Part No.:
- DG409DJZ
- Manufacturer:
- Renesas
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
DG409DJZ.pdf
- Description:
- IC SWITCH SP4T X 2 100OHM 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:522
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Product details
Overview
DG409DJZ from Renesas Electronics is a differential 4-channel CMOS analog multiplexer with bilateral signal switching, 100Ω max ON resistance at ±15V supplies, <250ns transition time, and operation across -40°C to +85°C for data acquisition and audio routing applications.
For engineers reviewing the DG409DJZ datasheet, DG409DJZ pinout, DG409DJZ application, or DG409DJZ equivalent, this page delivers verified specifications, package mapping, real-world use scenarios, and validated alternative options for industrial and test equipment design.
Technical Context
The DG409DJZ implements a TTL/CMOS-compatible 2-bit decode logic (A0/A1) controlling four matched differential switch pairs (S1A/S1B through S4A/S4B), each with symmetrical ON-resistance and low charge injection (20pC typ). It features independent enable (EN) control and internal 5V reference for stable logic thresholds.
Designed as a drop-in upgrade for DG509A, it uses high-voltage silicon-gate process to achieve lower rDS(ON) variation (<15Ω matching), reduced latch-up risk via epitaxial isolation, and dual-supply support from ±5V to ±20V or single +5V to +34V operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Channel Configuration | Differential 4-channel (8 terminals: 4 input pairs + 2 outputs) |
| Max ON Resistance | 100Ω at ±15V - ensures minimal signal attenuation in precision analog paths |
| Transition Time | <250ns - enables fast channel switching in automated test systems |
| Charge Injection | 20pC typ - reduces error in sample-and-hold circuits without added compensation |
| Analog Signal Range | ±15V (bipolar) or 0–12V (single supply) - supports wide dynamic range sensing |
| Supply Voltage Range | ±5V to ±20V or +5V to +34V - accommodates legacy and modern rail requirements |
| Logic Compatibility | TTL/CMOS - interfaces directly with microcontrollers and FPGAs without level shifters |
Pinout & Package
Package: 16-lead PDIP (Plastic Dual-In-Line), Pb-free, RoHS-compliant (PKG DWG # E16.3), suitable for through-hole wave solder only.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, A0 | Logic Decode Input (LSB) | Selects channel pair 0–3 when combined with A1; drives internal decoder |
| 2, EN | Enable Input | High-active control: disables all switches when low, enabling multi-device bus sharing |
| 3, V− | Negative Supply Terminal | Bias reference for analog path; must be ≤ V+ − 44V per absolute max rating |
| 4–7, S1A–S4A | Positive-side Source Inputs | Four analog inputs for differential pair A (e.g., sensor+, signal+, etc.) |
| 8, DA | Positive-side Drain Output | Common output node for all SxA channels; bidirectional conduction path |
| 9, DB | Negative-side Drain Output | Common output node for all SxB channels; completes differential signal path |
| 10–13, S4B–S1B | Negative-side Source Inputs | Four complementary analog inputs for differential pair B (e.g., sensor−, signal−) |
| 14, V+ | Positive Supply Terminal | Substrate bias and power rail; ties to highest potential in bipolar operation |
| 15, GND | Logic Ground Reference | Common return for digital inputs (EN, A0, A1); isolated from analog ground in layout |
| 16, A1 | Logic Decode Input (MSB) | Completes 2-bit address for selecting one of four differential channel pairs |
Key Features
| Feature | Design Value |
|---|---|
| Bilateral analog switching | Enables AC-coupled and bidirectional signal routing without polarity constraints |
| Low ON-resistance matching | ΔrDS(ON) ≤ 15Ω ensures consistent gain/attenuation across all 4 differential channels |
| Break-before-make timing | tOPEN ≥ 10ns prevents momentary shorting during channel transitions |
| Split or single supply operation | Eliminates need for external level-shifting circuitry in mixed-rail systems |
| Pb-free + anneal RoHS compliance | Matte tin termination compatible with SnPb and Pb-free soldering processes |
Applications
| Audio Switching Systems | Data Acquisition Systems |
|---|---|
Use Scenario: Routing multiple microphone or line-level inputs to a shared ADC in professional audio mixers. IC Role / Device Role / Timing Role: Differential analog multiplexer providing noise-rejecting signal selection before digitization. Use Value: 20pC charge injection minimizes hold-step error; ±15V range preserves full dynamic headroom. | Use Scenario: Scanning 8 thermocouple or strain gauge sensors into a single precision instrumentation amplifier. IC Role / Device Role / Timing Role: High-isolation (−75dB @ 100kHz), low-leakage (≤5nA) analog front-end selector. Use Value: 100Ω rDS(ON) and <250ns tTRANS support 10kSPS multiplexed sampling without settling penalty. |
| Automatic Test Equipment | Sample and Hold Circuits |
Use Scenario: Configuring stimulus/sense paths between DUT and measurement instruments in benchtop ATE platforms. IC Role / Device Role / Timing Role: Fast-switching, low-crosstalk (−75dB) differential switch enabling multi-point calibration sequences. Use Value: Break-before-make interval >10ns prevents transient shorts; TTL/CMOS compatibility simplifies controller interface. | Use Scenario: Selecting between multiple analog sources prior to capture by a high-speed sample-and-hold amplifier. IC Role / Device Role / Timing Role: Low-charge-injection analog gate minimizing aperture error during acquisition phase. Use Value: 20pC typical Q reduces voltage step on 10nF hold capacitor to <2mV - avoids post-acquisition correction. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar analog multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADG409BRZ | 16-lead SOIC; 75Ω max rDS(ON); 180ns tTRANS; requires ±15V or +12V single supply | Lower ON resistance but no PDIP option; higher leakage (10nA max ID(OFF)) at full temp range | Preferred for space-constrained PCBs where SOIC fits and tighter rDS(ON) tolerance is critical |
| MAX4052ACPP+ | 16-lead PDIP; 120Ω max rDS(ON); 200ns tTRANS; ±15V or +5V to +30V supply | Higher ON resistance and wider rDS(ON) spread (ΔrDS(ON) = 35Ω); same pinout but different truth table (active-low EN) | Acceptable for cost-sensitive designs where 120Ω rDS(ON) and inverted EN logic are acceptable |
Compared with ADG409BRZ and MAX4052ACPP+, the DG409DJZ offers superior channel matching (≤15Ω ΔrDS(ON)), industry-standard PDIP packaging, and guaranteed 100Ω rDS(ON) performance across −40°C to +85°C - making it optimal for legacy-compatible, high-precision analog routing.
Availability
DG409DJZ is available at Aetrix Electronics and suitable for data acquisition systems, audio switching systems, and automatic testers requiring stable component supply and long-term industrial availability.
Supply support for DG409DJZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT applications.
The DG409DJZ belongs to Renesas' legacy analog switch portfolio designed for high-reliability signal routing in test, measurement, and industrial control systems where robustness, wide supply range, and proven field reliability are essential.
FAQ
What is the maximum analog signal voltage range supported by the DG409DJZ?
The DG409DJZ supports an analog signal range of ±15V under bipolar supply conditions (V+ = +15V, V− = −15V) and 0–12V under single-supply operation (V+ = 12V, V− = 0V). These ranges are specified in the Electrical Specifications table on page 4 of the FN3283 datasheet and reflect the device's ability to pass signals without distortion or clipping within those bounds. The DG409DJZ maintains low ON-resistance and low leakage across these full ranges.
Does the DG409DJZ require external pull-up resistors on its digital control lines?
No, the DG409DJZ does not require external pull-up resistors on A0, A1, or EN. Its digital inputs are TTL/CMOS compatible with guaranteed logic thresholds (VAL ≤ 0.8V, VAH ≥ 2.4V) and low input current (±10μA max), allowing direct connection to microcontroller GPIOs or FPGA outputs. The internal 5V reference and protection diodes eliminate the need for external biasing - confirmed in the "Digital Input Characteristics" section of the FN3283 datasheet.
Can the DG409DJZ be used with a single +5V supply?
Yes, the DG409DJZ operates with a single +5V supply (V+ = +5V, V− = 0V), supporting analog signals from 0V to approximately +3.5V. While the datasheet specifies full performance (e.g., 100Ω rDS(ON), <250ns tTRANS) at ±15V or +12V, the Absolute Maximum Ratings confirm V+ to V− ≤ 44V and minimum functional supply of +5V. Page 5 lists single-supply test conditions confirming functionality at +12V; +5V operation is viable but may increase rDS(ON) and reduce bandwidth.
What is the thermal resistance (θJA) of the DG409DJZ in its PDIP package?
For the DG409DJZ in its 16-lead PDIP package (PKG DWG # E16.3), the typical junction-to-ambient thermal resistance (θJA) is 90°C/W, as specified in the "Thermal Information" table on page 4 of the FN3283 datasheet. This value assumes mounting on an evaluation PCB in free air and is critical for calculating junction temperature rise under load - for example, at 1mA channel current and 100Ω rDS(ON), power dissipation remains well below thermal limits even at +85°C ambient.
How does the DG409DJZ differ from the DG408DJZ in terms of channel architecture?
The DG409DJZ implements a differential 4-channel architecture (four matched switch pairs: S1A/S1B through S4A/S4B feeding two outputs DA and DB), whereas the DG408DJZ is a single-ended 8-channel multiplexer (eight inputs S1–S8 feeding one output D). This structural difference makes the DG409DJZ ideal for noise-immune differential signaling, while the DG408DJZ suits unbalanced, high-channel-count routing. Pinouts, truth tables, and internal decode logic are distinct - confirmed in Figures 1A/B and Truth Tables on pages 2–3 of FN3283.
DG409DJZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Obsolete
- Switch Circuit:
- SP4T
- Multiplexer/Demultiplexer Circuit:
- 4:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 100Ohm
- Channel-to-Channel Matching (ΔRon):
- 15Ohm (Max)
- Voltage - Supply, Single (V+):
- 5V ~ 34V
- Voltage - Supply, Dual (V±):
- ±5V ~ 20V
- Switch Time (Ton, Toff) (Max):
- 150ns, 150ns
- -3db Bandwidth:
- -
- Charge Injection:
- 20pC
- Channel Capacitance (CS(off), CD(off)):
- 3pF, 14pF
- Current - Leakage (IS(off)) (Max):
- 500pA
- Crosstalk:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
DG409DJZ FAQ
1.How can I place an order for DG409DJZ through Aetrix?
Please submit a Request for Quotation (RFQ) for DG409DJZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG409DJZ reliable?
The price and inventory of DG409DJZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG409DJZ is usually 5 days.
3.What payment methods are accepted for DG409DJZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG409DJZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG409DJZ?
DG409DJZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG409DJZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG409DJZ?
For technical support, including DG409DJZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG409DJZ requirements.
6.How does Aetrix verify that DG409DJZ is sourced from the original manufacturer or authorized distributors?
All DG409DJZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG409DJZ meets industry standards.
7.What is the process for return or replacement of DG409DJZ?
All DG409DJZ units undergo pre-shipment inspection (PSI). If there is an issue with DG409DJZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG409DJZ part is unused and in its original packaging.
Return procedure for DG409DJZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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