Analog Devices Inc./Maxim Integrated DG529CJ+
- Part No.:
- DG529CJ+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Package:
- 18-DIP (0.300", 7.62mm)
- Datasheet:
-
DG529CJ+.pdf
- Description:
- IC SWITCH SP4T X 2 450OHM 18DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,721
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DG529CJ+ from Maxim Integrated is a differential 2-of-8 CMOS analog multiplexer with on-board address latches, break-before-make switching, ±4.5V to ±20V dual-supply or +5V to +30V single-supply operation, and TTL/CMOS-compatible digital inputs - designed for precision data-acquisition systems requiring channel isolation and microprocessor bus interfacing.
For engineers reviewing the DG529CJ+ datasheet, DG529CJ+ pinout, DG529CJ+ application, or DG529CJ+ equivalent, key selection criteria include its differential input architecture, 400Ω max rDS(ON), 0.2µs break-before-make interval, 4pC charge injection, and compatibility with legacy DG529 and ADG529 families in 18-pin plastic DIP packaging.
Technical Context
The DG529CJ+ implements a latch-based decoding architecture with A0/A1 address inputs, EN enable, WR write strobe, and RS reset control - enabling transparent or latched operation modes. Its internal parallel N/P MOSFET switch structure supports bidirectional analog signal routing across four differential pairs (IN1A/IN1B through IN4A/IN4B).
It features dual-mode digital interface logic: TTL-compatible thresholds (~1.6V) with -3mV/°C tempco, ESD protection via 30V zener clamps, and ±2V overvoltage tolerance on digital inputs. Analog signal range spans V– to V+, with guaranteed performance from 0°C to +70°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Analog Signal Range | V– to V+ - supports rail-to-rail analog switching without clipping when supplies are properly biased |
| rDS(ON) Max | 400Ω - ensures low insertion loss and minimal gain error in precision measurement paths |
| Break-Before-Make Interval | 0.2µs - prevents momentary shorting between differential input pairs during channel switching |
| Charge Injection | 4pC - limits voltage glitch at output during switching, critical for high-resolution ADC front-ends |
| Supply Range | ±4.5V to ±20V dual or +5V to +30V single - enables flexible system-level power architecture design |
| Logic Compatibility | TTL and CMOS - eliminates need for level-shifting circuitry in mixed-signal microprocessor systems |
| Leakage Current (ID(OFF)) | ±10nA max - preserves signal integrity in high-impedance sensor interfaces and sample-hold circuits |
Pinout & Package
Package: 18-pin plastic DIP (0.300-inch width), JEDEC MS-001, operating temperature range 0°C to +70°C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (RS) | Reset Strobe Input | Active-low signal that clears all latches and disables all channels simultaneously |
| 2 (A1) | Address Bit 1 | Binary select line determining differential pair (1–4); used with A0 for 2-bit decode |
| 3 (GND) | Analog/Digital Ground | Common reference for analog signals and digital logic; must be low-impedance |
| 4 (V+) | Positive Supply Rail | Provides power to internal circuitry and defines upper analog signal limit |
| 5 (S1B) | Differential Output B (Channel 1) | Complementary output terminal of first differential pair; routed with S1A |
| 6 (S2B) | Differential Output B (Channel 2) | Complementary output terminal of second differential pair; routed with S2A |
| 7 (S3B) | Differential Output B (Channel 3) | Complementary output terminal of third differential pair; routed with S3A |
| 8 (S4B) | Differential Output B (Channel 4) | Complementary output terminal of fourth differential pair; routed with S4A |
| 9 (DB) | Common Differential Output B | Shared output node for all SxB terminals; connects to external differential receiver |
| 10 (WR) | Write Strobe Input | Latches current A0/A1 state on falling edge; enables transparent or stored operation mode |
| 11 (A0) | Address Bit 0 | Binary select line determining differential pair (1–4); used with A1 for 2-bit decode |
| 12 (EN) | Enable Input | Active-high control that globally enables/disables all switches under program control |
| 13 (V–) | Negative Supply Rail | Defines lower analog signal limit; required for bipolar or negative-range signal handling |
| 14 (S1A) | Differential Output A (Channel 1) | Primary output terminal of first differential pair; routed with S1B |
| 15 (S2A) | Differential Output A (Channel 2) | Primary output terminal of second differential pair; routed with S2B |
| 16 (S3A) | Differential Output A (Channel 3) | Primary output terminal of third differential pair; routed with S3B |
| 17 (S4A) | Differential Output A (Channel 4) | Primary output terminal of fourth differential pair; routed with S4B |
| 18 (DA) | Common Differential Output A | Shared output node for all SxA terminals; connects to external differential receiver |
Key Features
| Feature | Design Value |
|---|---|
| On-board address latches | Eliminates need for external latch ICs and reduces PCB footprint in µP-controlled systems |
| Break-before-make switching | Prevents cross-conduction between differential input sources during channel transitions |
| Differential 2-of-8 architecture | Routes matched complementary signals per channel - essential for noise-rejecting data acquisition |
| Microprocessor-bus compatible timing | Supports direct connection to 8080/8085-style buses with WR/RS strobes and no glue logic |
| Pin and electrical compatibility | Drop-in replacement for industry-standard DG529 and ADG529 in 18-pin DIP layout |
Applications
| Data-Acquisition Systems | Automatic Test Equipment |
|---|---|
Use Scenario: Multiplexing multiple sensor outputs (e.g., thermocouples, strain gauges) into a single high-resolution ADC. IC Role / Device Role / Timing Role: Differential analog multiplexer providing channel selection, break-before-make isolation, and low-charge-injection switching. Use Value: Enables 16-bit+ measurement accuracy by minimizing crosstalk, offset drift, and switching transients across channels. | Use Scenario: Routing stimulus and response signals between DUT and instrumentation in automated test racks. IC Role / Device Role / Timing Role: Bidirectional differential switch matrix supporting programmable signal path configuration under GPIB or PXI control. Use Value: Reduces test head complexity with latched addressing and simultaneous differential path setup for multi-point measurements. |
| Avionics and Military Systems | Communication Systems |
Use Scenario: Selecting redundant analog telemetry channels in flight control or navigation subsystems. IC Role / Device Role / Timing Role: Radiation-tolerant (CERDIP variants available), latch-protected analog switch ensuring fail-safe channel management. Use Value: Maintains signal integrity and deterministic switching behavior under wide temperature (-55°C to +125°C) and supply-voltage variation. | Use Scenario: Configuring differential baseband signal paths in software-defined radio (SDR) front-ends. IC Role / Device Role / Timing Role: Low-distortion analog multiplexer routing I/Q signals between filters, amplifiers, and ADCs. Use Value: Preserves phase matching and common-mode rejection ratio (CMRR) across switched differential paths up to 140kHz. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar differential multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADG529FKNZ | Higher rDS(ON) (600Ω typ), wider temp range (–40°C to +125°C), SOIC-18 package | Better suited for industrial environments requiring extended temperature operation and RoHS compliance | Select when higher temperature rating and lead-free packaging outweigh need for lowest on-resistance |
| DG529DJ+ | Same die, –40°C to +85°C temp grade, 18-pin plastic DIP | Direct functional and pinout match with enhanced industrial temperature support | Choose for drop-in upgrade where extended temperature range is required without layout change |
Compared with DG529CJ+, ADG529FKNZ offers broader temperature capability but higher on-resistance, while DG529DJ+ provides identical functionality with extended operating range - making it the preferred upgrade path for new designs targeting industrial reliability.
Availability
DG529CJ+ is available at Aetrix Electronics and suitable for data-acquisition systems, automatic test equipment, and avionics applications requiring stable component supply, long-term obsolescence management, and traceable sourcing from authorized channels.
Supply support for DG529CJ+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and power management ICs for industrial, communications, and computing markets.
The DG529CJ+ belongs to Maxim's legacy precision analog multiplexer product line, engineered for high-fidelity signal routing in microprocessor-controlled measurement and control systems where latchability, low leakage, and differential integrity are critical.
FAQ
What is the maximum analog signal voltage range supported by the DG529CJ+?
The DG529CJ+ supports an analog signal range from V– to V+. With ±15V supplies, it handles ±15V signals; with +15V/–5V asymmetrical supplies, it routes signals from –5V to +15V. The DG529CJ+ datasheet specifies absolute maximum analog voltage as ±15V under standard operating conditions, and the device maintains specified rDS(ON) and leakage performance across this full range when powered within its supply limits.
Does the DG529CJ+ require external latching circuitry when used with a microprocessor?
No, the DG529CJ+ does not require external latching circuitry. It integrates on-board address latches controlled by WR (write) and RS (reset) strobes, allowing it to retain channel selection independently of continuous address bus drive. This feature simplifies interface with 8080/8085-style microprocessors and eliminates the need for external 74HC373 or similar latch ICs in the DG529CJ+ signal path.
How does the break-before-make function operate in the DG529CJ+?
The DG529CJ+ guarantees a minimum 0.2µs break interval between channel disconnect and reconnect during address changes. This timing prevents momentary shorting between differential input pairs (e.g., IN1A/IN1B to IN2A/IN2B), preserving signal integrity in sensitive measurement circuits. The interval is internally generated and independent of external timing - no additional delay circuitry is needed to ensure safe switching in the DG529CJ+.
Can the DG529CJ+ operate from a single +5V supply?
Yes, the DG529CJ+ operates from a single +5V to +30V supply. When using +5V, connect V– to GND. Digital inputs remain TTL-compatible (threshold ~1.5V), and analog range becomes 0V to +5V. Note that rDS(ON) increases and switching speed decreases versus ±15V operation, but break-before-make action and latch functionality remain fully functional across the entire single-supply range for the DG529CJ+.
Is the DG529CJ+ pin-compatible with the ADG529 series?
Yes, the DG529CJ+ is pin and electrically compatible with the ADG529 family in 18-pin DIP packaging, as confirmed in the Maxim datasheet. Both share identical pinout, supply requirements, logic thresholds, and switching characteristics. However, ADG529 devices exhibit higher typical rDS(ON) (600Ω vs. 400Ω for DG529CJ+) and different charge injection (6pC vs. 4pC), so system-level validation is recommended before substitution in high-precision DG529CJ+ applications.
DG529CJ+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Packaging:
- Tube
- Product Status:
- Active
- Switch Circuit:
- SP4T
- Multiplexer/Demultiplexer Circuit:
- 4:1
- Number of Circuits:
- 2
- On-State Resistance (Max):
- 450Ohm
- Channel-to-Channel Matching (ΔRon):
- 27Ohm
- Voltage - Supply, Single (V+):
- 5V ~ 30V
- Voltage - Supply, Dual (V±):
- ±4.5V ~ 20V
- Switch Time (Ton, Toff) (Max):
- 1.5µs, 1.5µs
- -3db Bandwidth:
- -
- Charge Injection:
- 4pC
- Channel Capacitance (CS(off), CD(off)):
- 5pF, 25pF
- Current - Leakage (IS(off)) (Max):
- 5nA
- Crosstalk:
- -
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 18-PDIP
DG529CJ+ FAQ
1.How can I place an order for DG529CJ+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DG529CJ+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG529CJ+ reliable?
The price and inventory of DG529CJ+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG529CJ+ is usually 5 days.
3.What payment methods are accepted for DG529CJ+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG529CJ+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG529CJ+?
DG529CJ+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG529CJ+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG529CJ+?
For technical support, including DG529CJ+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG529CJ+ requirements.
6.How does Aetrix verify that DG529CJ+ is sourced from the original manufacturer or authorized distributors?
All DG529CJ+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG529CJ+ meets industry standards.
7.What is the process for return or replacement of DG529CJ+?
All DG529CJ+ units undergo pre-shipment inspection (PSI). If there is an issue with DG529CJ+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG529CJ+ part is unused and in its original packaging.
Return procedure for DG529CJ+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DG529CJ+ Tags

-
SN74LVC1G3157DBVR
Texas Instruments
-
SN74LVC1G66DBVR
Texas Instruments
-
SN74LVC1G66DCKR
Texas Instruments

-
SN74LVC1G3157DSFR
Texas Instruments

-
1P1G3157QDCKRQ1
Texas Instruments

-
SN74LVC2G66DCUR
Texas Instruments
-
SN74LV4052APWR
Texas Instruments

-
74HC4051D,653
Nexperia USA Inc.
-
SN74LV4051APWR
Texas Instruments
-
CD74HC4052PWR
Texas Instruments
-
CD74HC4051PWR
Texas Instruments
-
TS5A3166DBVR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

