Vishay Siliconix DG9461DY-E3
- Part No.:
- DG9461DY-E3
- Manufacturer:
- Vishay Siliconix
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DG9461DY-E3.pdf
- Description:
- IC SWITCH SPDT X 1 60OHM 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,064
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Product details
Overview
DG9461DY-E3 from Vishay Siliconix is a low-voltage single-pole/double-throw (SPDT) CMOS analog switch optimized for battery-powered systems. It operates from +2.7 V to +5 V, delivers 40 Ω typical on-resistance at 5 V, achieves 35 ns turn-on and 20 ns turn-off times, and features 1 pC charge injection - enabling high-accuracy signal routing in portable test equipment and cellular handsets.
For engineers reviewing the DG9461DY-E3 datasheet, DG9461DY-E3 pinout, DG9461DY-E3 application, or DG9461DY-E3 equivalent, key selection criteria include guaranteed break-before-make timing, TSOP-6/SOIC-8 package options, ±20 mA continuous current rating, -74 dB off-isolation at 1 MHz, and RoHS-compliant Pb-free termination per ordering suffix E3.
Technical Context
The DG9461DY-E3 implements a monolithic CMOS SPDT switch architecture with epitaxial latchup protection and BCD-15 process technology. Its logic interface accepts TTL/CMOS-compatible inputs (0.8 V low, 2.4 V high), and internal clamping diodes limit analog signals to V+ ± 0.3 V.
Break-before-make switching is guaranteed with ≤10 ns transition interval, and bidirectional conduction ensures equal performance regardless of signal direction. The device blocks up to the supply rail when off and supports full-rail analog signal ranges from 0 V to V+.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | +2.7 V to +12 V - supports 3 V and 5 V logic systems with margin for transient spikes |
| rDS(on) | 30 Ω typical at V+ = 5 V - minimizes signal attenuation and voltage drop in precision analog paths |
| tON / tOFF | 35 ns / 20 ns at V+ = 5 V - enables high-speed multiplexing in data acquisition and communication interfaces |
| Charge Injection | 1 pC - reduces settling error in sample-and-hold and ADC front-end circuits |
| Off-Isolation | -74 dB at 1 MHz - suppresses crosstalk between channels in multi-signal routing applications |
| ESD Protection | >2000 V HBM (Method 3015.7) - enhances robustness during board handling and system integration |
| Leakage Current | 200 pA max ICOM(on) - preserves signal integrity in high-impedance sensor and medical monitoring circuits |
Pinout & Package
DG9461DY-E3 is packaged in an 8-pin narrow-body SOIC (SOIC-8) with standard 1.27 mm pitch. Pin 1 is marked by a notch or dot; pin numbering follows JEDEC MS-012.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (IN) | Digital control input | Active-high logic: '1' ≥ 2.4 V selects NO path; '0' ≤ 0.8 V selects NC path |
| 2 (NO) | Normally open switch terminal | Connects to COM only when IN = high; supports bidirectional analog signal flow |
| 3 (NC) | Normally closed switch terminal | Connects to COM only when IN = low; isolated from COM during transition |
| 4 (GND) | Analog and digital ground reference | Common return for power, logic, and signal paths; must be low-impedance |
| 5 (COM) | Common analog port | Single-pole connection point; routes signal to either NO or NC based on IN state |
| 6 (V+) | Positive supply rail | Provides operating power and defines analog signal ceiling (0 V to V+ range) |
| 7 (NC) | No-connect terminal | Internally unconnected; must remain floating or tied to GND per layout best practice |
| 8 (NC) | No-connect terminal | Internally unconnected; no electrical function; avoid routing traces to this pin |
Key Features
| Feature | Design Value |
|---|---|
| Guaranteed break-before-make | Ensures no momentary short between NO and NC paths during switching - critical for avoiding signal glitches in audio and RF routing |
| Bidirectional analog conduction | Enables identical on-resistance and capacitance whether signal flows COM→NO or NO→COM - simplifies PCB layout and system design |
| Low 1 pC charge injection | Minimizes voltage step errors in sample-and-hold and switched-capacitor circuits - improves DC accuracy and settling time |
| TSOP-6 and SOIC-8 packaging | SOIC-8 variant (DG9461DY-E3) offers proven manufacturability and thermal performance; TSOP-6 option saves board space in ultra-portable designs |
| 2000 V HBM ESD rating | Reduces risk of field failure during assembly and end-user handling without requiring external protection components |
Applications
| Battery-Powered Instrumentation | Portable Communications |
|---|---|
Use Scenario: Signal routing in handheld multimeters and portable oscilloscope front-ends where low power and minimal signal distortion are essential. IC Role / Device Role / Timing Role: SPDT analog switch selecting between multiple sensor inputs or calibration references under microcontroller control. Use Value: 40 Ω rDS(on) and 1 pC charge injection preserve measurement accuracy; 35 ns switching enables rapid channel scanning without added latency. | Use Scenario: Audio path selection in dual-SIM smartphones supporting simultaneous voice and VoLTE calls. IC Role / Device Role / Timing Role: Low-distortion analog switch isolating microphone and speaker paths during call handover or mode switching. Use Value: -74 dB off-isolation prevents audible crosstalk; 200 pA leakage avoids DC bias shifts in electret microphone bias networks. |
| Medical Monitoring Devices | Industrial Data Acquisition |
Use Scenario: Multiplexing ECG, SpO₂, and temperature sensor signals into a shared ADC in wearable patient monitors. IC Role / Device Role / Timing Role: Precision analog switch providing rail-to-rail signal pass-through with negligible gain error or offset drift. Use Value: Full 0–5 V analog range compatibility and 200 pA max on-state leakage maintain clinical-grade signal fidelity over temperature. | Use Scenario: Channel selection in modular PLC I/O modules interfacing with thermocouples, RTDs, and 4–20 mA transmitters. IC Role / Device Role / Timing Role: High-reliability SPDT switch enabling automatic calibration loopback and sensor redundancy switching. Use Value: Guaranteed break-before-make prevents short-circuits during hot-swap events; 2000 V ESD withstand protects against factory and field electrostatic discharge. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SPDT analog switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX4617EUT+T | Higher 60 Ω rDS(on) at 5 V; 50 ns tON; same SOIC-8 package | Lower bandwidth and higher on-resistance limit use in high-fidelity audio or fast data acquisition | Select when cost sensitivity outweighs speed/accuracy requirements and existing layout accommodates higher on-resistance |
| ADG849BRMZ-REEL | Lower 0.5 pC charge injection; 25 Ω rDS(on); 16-lead TSSOP package | Smaller signal error but larger footprint and different pinout require PCB redesign | Prefer for ultra-low-error sample-and-hold or precision instrumentation where layout revision is feasible |
Compared with MAX4617EUT+T and ADG849BRMZ-REEL, the DG9461DY-E3 provides optimal balance of speed (35 ns), on-resistance (30 Ω), and compact SOIC-8 form factor - making it ideal for space-constrained, battery-operated systems needing reliable, production-ready analog switching without layout change.
Availability
DG9461DY-E3 is available at Aetrix Electronics and suitable for battery-operated instrumentation, portable communications, and industrial data acquisition requiring stable component supply across extended temperature ranges (-40 °C to +85 °C).
Supply support for DG9461DY-E3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Vishay Siliconix is a global semiconductor manufacturer specializing in discrete MOSFETs, diodes, optoelectronics, and analog switches built on advanced BCD processes.
The DG9461DY-E3 belongs to Vishay's low-voltage analog switch product line, engineered specifically for portable, battery-powered applications demanding low on-resistance, fast switching, and minimal charge injection.
FAQ
What is the maximum analog signal voltage supported by the DG9461DY-E3?
The DG9461DY-E3 supports analog signals from 0 V to V+, where V+ ranges from +2.7 V to +12 V. At V+ = 5 V, the full analog range is 0–5 V. Signals exceeding V+ or going below GND are clamped by internal diodes - forward current must be limited to ±20 mA continuous to avoid damage. This rail-to-rail capability makes DG9461DY-E3 suitable for direct interfacing with ADCs and DACs operating at the same supply.
Does the DG9461DY-E3 require external pull-up or pull-down resistors on the IN pin?
No, the DG9461DY-E3 does not require external pull-up or pull-down resistors on the IN pin. Its TTL/CMOS-compatible input threshold is defined as logic low ≤ 0.8 V and logic high ≥ 2.4 V, with input current limited to ±1 µA across temperature. Microcontroller GPIOs or FPGA outputs driving DG9461DY-E3 directly meet these levels without additional biasing - simplifying interface design and reducing BOM count.
Is break-before-make timing guaranteed for the DG9461DY-E3, and what is its typical value?
Yes, break-before-make timing is guaranteed for the DG9461DY-E3. The datasheet specifies a maximum break-before-make interval (td) of 10 ns at V+ = 5 V and room temperature. This guarantee prevents momentary shorting between NO and NC paths during state transitions - a critical requirement in audio routing, RF switching, and safety-critical sensor multiplexing where signal integrity must be preserved across all operating conditions.
What is the thermal derating behavior of the DG9461DY-E3 above 75 °C?
The DG9461DY-E3 requires thermal derating above 75 °C at 6.5 mW/°C. Its SOIC-8 package has a rated power dissipation of 400 mW at ≤75 °C ambient. Above that, allowable power drops linearly - e.g., at 100 °C ambient, maximum dissipation is reduced to 400 mW − (25 °C × 6.5 mW/°C) = 237.5 mW. Designers must verify junction temperature using θJA (typically 120 °C/W for SOIC-8) and ensure operation remains within -40 °C to +85 °C specified range.
How does the DG9461DY-E3 handle ESD events, and is external protection needed?
The DG9461DY-E3 incorporates on-die ESD protection rated >2000 V per Human Body Model (HBM) Method 3015.7. This level meets typical IEC 61000-4-2 Level 2 requirements for system-level immunity and eliminates the need for external TVS diodes in most board-level applications. However, in high-risk environments (e.g., handheld devices with exposed connectors), adding a 0402-size 5 V TVS remains a prudent design margin - especially where repeated contact discharge is expected beyond lab testing conditions.
DG9461DY-E3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Vishay Siliconix
- Series:
- -
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Switch Circuit:
- SPDT
- Multiplexer/Demultiplexer Circuit:
- 2:1
- Number of Circuits:
- 1
- On-State Resistance (Max):
- 60Ohm
- Channel-to-Channel Matching (ΔRon):
- 400mOhm
- Voltage - Supply, Single (V+):
- 2.7V ~ 5V
- Voltage - Supply, Dual (V±):
- -
- Switch Time (Ton, Toff) (Max):
- 75ns, 50ns
- -3db Bandwidth:
- -
- Charge Injection:
- 2pC
- Channel Capacitance (CS(off), CD(off)):
- 7pF
- Current - Leakage (IS(off)) (Max):
- 100pA
- Crosstalk:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DG9461DY-E3 FAQ
1.How can I place an order for DG9461DY-E3 through Aetrix?
Please submit a Request for Quotation (RFQ) for DG9461DY-E3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DG9461DY-E3 reliable?
The price and inventory of DG9461DY-E3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DG9461DY-E3 is usually 5 days.
3.What payment methods are accepted for DG9461DY-E3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DG9461DY-E3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DG9461DY-E3?
DG9461DY-E3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DG9461DY-E3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DG9461DY-E3?
For technical support, including DG9461DY-E3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DG9461DY-E3 requirements.
6.How does Aetrix verify that DG9461DY-E3 is sourced from the original manufacturer or authorized distributors?
All DG9461DY-E3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DG9461DY-E3 meets industry standards.
7.What is the process for return or replacement of DG9461DY-E3?
All DG9461DY-E3 units undergo pre-shipment inspection (PSI). If there is an issue with DG9461DY-E3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DG9461DY-E3 part is unused and in its original packaging.
Return procedure for DG9461DY-E3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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