Texas Instruments DIR9001PWR
- Part No.:
- DIR9001PWR
- Manufacturer:
- Texas Instruments
- Category:
- Audio Special Purpose
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DIR9001PWR.pdf
- Description:
- IC AUDIO RECEIVER 28TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:7,534
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DIR9001PWR from Texas Instruments is a 24-bit digital audio interface receiver IC that recovers low-jitter system clocks (50 ps rms) and decodes biphase-encoded S/PDIF, AES3, or EBU signals across 28–108 kHz sampling frequencies. It outputs I²S/Left-Justified/Right-Justified serial audio data with dedicated channel-status (COUT), user-data (UOUT), and pre-emphasis (EMPH) pins, and supports automotive-grade operation from –40°C to 85°C.
For engineers reviewing the DIR9001PWR datasheet, DIR9001PWR pinout, DIR9001PWR application, or DIR9001PWR equivalent, this device serves as a drop-in replacement for DIR1703 in AV receivers, car audio systems, and digital TVs-offering improved IEC60958-3 jitter tolerance, wider supply range (2.7–3.6 V), and extended temperature capability without requiring external clock sources for basic decode operation.
Technical Context
The DIR9001PWR implements a conventional PLL-based clock recovery architecture-not SpAct™-with VCO-based frequency synthesis locked to incoming biphase data. Its internal sampling-frequency calculator requires an optional 24.576-MHz XTI source, while standalone decode uses only RXIN input and on-chip loop filter connected between FILT and AGND.
Hardware control is fully pin-driven: PSCK0/PSCK1 select SCKO output at 128fS, 256fS, 384fS, or 512fS; FMT0/FMT1 configure data format (I²S, left/right-justified); CKSEL switches between PLL-derived and XTI-derived system clock; RST provides active-low asynchronous reset with defined output states during assertion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Biphase Input Range | 28 kHz to 108 kHz continuous sampling frequency - supports all standard audio rates including 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz |
| Recovered Clock Jitter | 50 ps rms (typical) - meets low-jitter requirements for high-fidelity audio DAC clocking |
| Jitter Tolerance | IEC60958-3 compliant - ensures robust lock under real-world transmission impairments |
| Supply Voltage | 2.7 V to 3.6 V - enables direct interface with 3.3-V logic and automotive power rails |
| Operating Temperature | –40°C to +85°C - qualified for under-dash automotive audio and industrial embedded use |
| Digital Inputs | 5-V tolerant TTL - accepts standard optical receiver (TOSLINK) outputs without level-shifting |
| Output Formats | 24-bit I²S, 24-bit left-justified, 16-/24-bit right-justified - matches common audio codec interface requirements |
| Power Dissipation | 40–68 mW at 96 kHz - enables thermally constrained PCB layouts in compact AV modules |
Pinout & Package
DIR9001PWR is housed in a 28-pin TSSOP package (4.40 mm × 9.70 mm, 0.65 mm pitch) with separate analog (AGND/VCC) and digital (DGND/VDD) power domains to minimize noise coupling in sensitive audio signal paths.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RXIN | Biphase data input | 5-V tolerant TTL input accepting S/PDIF/AES3 signals directly from optical or coaxial receivers |
| SCKO | System clock output | CMOS output of recovered clock at 128fS–512fS; 10-pF load max; jitter ≤100 ps rms |
| BCKO | Bit clock output | 64fS bit clock synchronized to DOUT/LRCKO; 60 ns min pulse width; 20-pF load |
| LRCKO | Word clock output | Frame sync (fS) signal indicating left/right channel boundary; aligned to DOUT MSB |
| DOUT | Audio data output | 16-/24-bit PCM data, MSB-first, format selected by FMT0/FMT1; synchronized to BCKO/LRCKO |
| COUT | Channel status output | Serial stream of IEC60958 channel status bits, synchronized to LRCKO transitions |
| UOUT | User data output | Serial stream of user-defined bits, synchronized to LRCKO transitions |
| ERROR | PLL/data error flag | Active-high CMOS output signaling PLL unlock or biphase parity error |
| CLKST | Clock transition indicator | Active-high pulse marking change in recovered clock frequency or source (PLL→XTI or vice versa) |
| FILT | Loop filter connection | Analog node connecting external RC filter to AGND - sets PLL bandwidth and stability |
| XTI/ XTO | Oscillator interface | XTI: input for 24.576-MHz crystal/resonator or external clock; XTO: buffered oscillator output |
| CKSEL | Clock source selector | Pulldown-input selecting PLL (low) or XTI (high) as SCKO source; no glitch-free switching guaranteed |
| RST | Reset control | Active-low TTL input requiring ≥100 ns pulse after VDD ≥2.7 V; forces all outputs to defined states |
| FMT0/FMT1 | Data format control | Pulldown inputs selecting I²S (00), left-justified (01), 24-bit right-justified (10), or 16-bit right-justified (11) |
| PSCK0/PSCK1 | SCKO frequency selection | Pulldown inputs setting SCKO to 128fS (00), 256fS (01), 384fS (10), or 512fS (11) |
| FSOUT0/FSOUT1 | Sampling frequency code | 2-bit binary output indicating detected fS range (e.g., 00 = 28–40 kHz, 11 = 80–108 kHz) |
| EMPH | Pre-emphasis flag | Indicates presence of 50 μs / 15 μs pre-emphasis in channel status data |
| AUDIO | Non-audio flag | Active-low signal indicating non-audio sample word (e.g., channel status, user data) |
| BFRAME | Block start indicator | Signals top of biphase frame (32-bit preamble); used for synchronization and error detection |
| VCC/AGND | Analog supply/ground | 3.3-V analog domain powering PLL, VCO, and analog front-end; must be filtered separately from digital rails |
| VDD/DGND | Digital supply/ground | 3.3-V digital domain powering logic, outputs, and interface circuitry; decoupling critical for low EMI |
| RSV | Reserved input | Must be tied to DGND; no internal function; leaving floating may cause undefined behavior |
Key Features
| Feature | Design Value |
|---|---|
| No external clock required for decode | Enables cost-effective S/PDIF receiver implementation using only RXIN input-no crystal or oscillator needed unless using sampling-frequency calculator or XTI clock output |
| IEC60958-3 jitter tolerance compliance | Guarantees reliable lock under standardized jitter stress conditions, eliminating need for external jitter cleaners in consumer audio designs |
| Dedicated channel-status and user-data outputs | Offloads microcontroller processing by providing COUT/UOUT streams synchronized to LRCKO, simplifying extraction of metadata in real time |
| Hardware-only configuration | Full functionality controlled via 5-V tolerant TTL pins (FMT0/FMT1/PSCK0/PSCK1/CKSEL/RST)-no firmware or I²C required for basic operation |
| Automotive temperature qualification | –40°C to +85°C operation enables deployment in vehicle infotainment head units and amplifier modules without derating or thermal management |
| Pin-compatible with DIR1703 | Direct replacement in existing designs with identical 28-pin TSSOP footprint and overlapping functionality-enables upgrade path with minimal layout changes |
Applications
| AV/DVD Receiver | Car Audio System |
|---|---|
Use Scenario: Receives digital audio from Blu-ray player or streaming box via coaxial S/PDIF into multi-channel AV processor. IC Role / Device Role / Timing Role: DIR9001PWR acts as primary S/PDIF receiver, recovering low-jitter master clock (256fS) and outputting I²S data to downstream DACs. Use Value: Eliminates need for external crystal and reduces BOM count by 2 components versus discrete PLL+decoder solutions. | Use Scenario: Interfaces optical TOSLINK output from head unit to DSP-based amplifier in premium vehicle audio system. IC Role / Device Role / Timing Role: DIR9001PWR receives 48 kHz/24-bit AES3 stream over fiber, outputs synchronized BCKO/LRCKO/DOUT to TI C5000 DSP. Use Value: 5-V tolerant RXIN accepts raw TOSLINK output without buffer; –40°C to +85°C rating ensures reliability in under-dash environment. |
| Digital Television | High-End PC Sound Card |
Use Scenario: Extracts stereo PCM from HDMI ARC or optical audio feed in smart TV mainboard. IC Role / Device Role / Timing Role: DIR9001PWR decodes biphase data, outputs 24-bit left-justified format to integrated audio codec, with EMPH and AUDIO flags routed to MCU for UI feedback. Use Value: Hardware-configurable FMT0/FMT1 pins allow fixed-format output without software overhead-critical for resource-constrained TV SoCs. | Use Scenario: Provides isolated, low-jitter digital audio input path on PCIe sound card supporting studio-grade recording. IC Role / Device Role / Timing Role: DIR9001PWR recovers 96 kHz clock with 50 ps jitter, feeding ultra-low-noise DAC; FSOUT0/FSOUT1 report sampling rate to host driver. Use Value: IEC60958-3 compliance ensures compatibility with professional audio sources; separate AGND/DGND planes reduce digital noise coupling into analog stages. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital audio interface receiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DIR1703PWR | Narrower supply (3.0–3.6 V), limited temp range (–25°C to 85°C), non-compliant with IEC60958-3 jitter tolerance, no 24.576-MHz calculator mode | Legacy designs where cost is prioritized over automotive qualification or jitter performance; lacks FSOUT0/FSOUT1 sampling-rate indication | Select DIR1703PWR only if existing design uses it and no upgrade path is planned-DIR9001PWR offers superior specs and full pin compatibility. |
| CS8416-CZZ | Supports AES3/SPDIF/I²S input; includes I²C interface for configuration; higher integration (no external loop filter needed); 5-V tolerant inputs but 3.3-V only outputs | Systems requiring programmable features (sample rate conversion, channel routing) or I²C-based host control instead of hardware pin-strapping | Choose CS8416-CZZ when flexibility and configurability outweigh cost and simplicity-DIR9001PWR excels in fixed-function, low-component-count implementations. |
Compared with DIR1703PWR and CS8416-CZZ, DIR9001PWR delivers optimal balance of automotive-grade reliability, hardware-only operation, and IEC60958-3 compliance-making it ideal for cost-sensitive, high-volume consumer and automotive audio receivers where deterministic timing and minimal firmware dependency are essential.
Availability
DIR9001PWR is available at Aetrix Electronics and suitable for AV receivers, car audio systems, and digital televisions requiring stable component supply, long-term lifecycle support, and automotive-qualified performance.
Supply support for DIR9001PWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions, with deep expertise in audio signal chain ICs and high-reliability automotive components.
The DIR9001PWR belongs to TI's digital audio interface receiver product line, engineered specifically for robust, low-jitter S/PDIF and AES3 decoding in cost-sensitive consumer and automotive audio systems without requiring microcontroller intervention.
FAQ
What is the minimum sampling frequency supported by the DIR9001PWR?
The DIR9001PWR supports a continuous biphase input sampling frequency range from 28 kHz to 108 kHz. This includes all standard audio rates such as 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The lower bound of 28 kHz enables compatibility with specialized professional audio equipment and legacy broadcast formats not covered by narrower-range receivers like the DIR1703PWR.
Does the DIR9001PWR require an external crystal or resonator to operate?
No, the DIR9001PWR does not require an external crystal or resonator for basic S/PDIF decode and clock recovery. It derives all necessary timing from the RXIN biphase input signal using its internal PLL. An external 24.576-MHz source on XTI is only needed if using the internal sampling-frequency calculator or generating a precise 24.576-MHz reference clock for peripheral devices.
How does the DIR9001PWR handle jitter in the input signal?
The DIR9001PWR complies with IEC60958-3 jitter tolerance requirements, ensuring reliable lock and clean recovered clock output even under specified jitter stress conditions. Its recovered system clock exhibits ≤50 ps rms jitter (typical), making it suitable for driving high-performance audio DACs without additional jitter cleaning circuitry.
Is the DIR9001PWR pin-compatible with the DIR1703PWR?
Yes, the DIR9001PWR is pin-compatible with the DIR1703PWR in the same 28-pin TSSOP package. Pin assignments are functionally equivalent per TI's documentation, enabling direct replacement in existing designs. However, DIR9001PWR adds enhanced features-including wider supply range, extended temperature rating, and IEC60958-3 compliance-without requiring PCB modifications.
What output data formats does the DIR9001PWR support?
The DIR9001PWR supports four serial audio data output formats selectable via FMT0 and FMT1 pins: 24-bit I²S (MSB-first), 24-bit left-justified (MSB-first), 24-bit right-justified (MSB-first), and 16-bit right-justified (MSB-first). All formats are synchronized to BCKO and LRCKO outputs, ensuring deterministic timing for interfacing with standard audio codecs and DSPs.
DIR9001PWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Audio Receiver
- Applications:
- Audio, Musical Instruments
- Number of Channels:
- 1
- Interface:
- I2S
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Specifications:
- 28kHz ~ 108kHz
- Mounting Type:
- Surface Mount
- Grade:
- Automotive
DIR9001PWR FAQ
1.How can I place an order for DIR9001PWR through Aetrix?
Please submit a Request for Quotation (RFQ) for DIR9001PWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DIR9001PWR reliable?
The price and inventory of DIR9001PWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DIR9001PWR is usually 5 days.
3.What payment methods are accepted for DIR9001PWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DIR9001PWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DIR9001PWR?
DIR9001PWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DIR9001PWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DIR9001PWR?
For technical support, including DIR9001PWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DIR9001PWR requirements.
6.How does Aetrix verify that DIR9001PWR is sourced from the original manufacturer or authorized distributors?
All DIR9001PWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DIR9001PWR meets industry standards.
7.What is the process for return or replacement of DIR9001PWR?
All DIR9001PWR units undergo pre-shipment inspection (PSI). If there is an issue with DIR9001PWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DIR9001PWR part is unused and in its original packaging.
Return procedure for DIR9001PWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DIR9001PWR Tags

-
SA571DR2G
onsemi

-
ADAU7002ACBZ-R7
Analog Devices Inc.

-
DRV135UA/2K5
Texas Instruments

-
DRV134UA/1K
Texas Instruments

-
DRV134PA
Texas Instruments

-
DRV134UA
Texas Instruments

-
DRV135UA
Texas Instruments

-
SA572DR2G
onsemi

-
PGA2311U/1K
Texas Instruments

-
SI8244BB-D-IS1R
Skyworks Solutions Inc.

-
CS8416K-CZZR
Cirrus Logic Inc.

-
SRC4392IPFBR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

