Texas Instruments DLPC3420ZVB

Overview

DLPC3420ZVB from Texas Instruments is a display controller IC designed to drive the DLP160AP 0.16-inch QnHD digital micromirror device (DMD), supporting up to 60 Hz input frame rates, 24-bit parallel/BT656/MIPI DSI input interfaces, and embedded eDRAM for frame buffering. It enables compact, low-power pico projection systems in mobile and wearable displays.

For engineers reviewing the DLPC3420ZVB datasheet, DLPC3420ZVB pinout, DLPC3420ZVB application, or DLPC3420ZVB equivalent, key selection considerations include DMD sub-LVDS interface timing compliance, MIPI DSI lane configuration (1–4 lanes at ≤470 Mbps/lane), CAIC-based power management, and co-design requirements with DLPA2000/DLPA2005 PMICs.

Technical Context

The DLPC3420ZVB implements a dual-path pixel interface architecture: high-speed sub-LVDS for DMD control (with configurable 16-bit write data lanes) and flexible host-side input via parallel (24-bit RGB/BT656) or MIPI DSI (Type 3, up to 4 lanes). It integrates a programmable degamma engine, 1D keystone correction, and color space conversion logic for real-time image preprocessing.

Its system-level timing control includes synchronized DMD parking via PARKZ, auto-initialization triggered by RESETZ, and host interrupt signaling through HOST_IRQ. The controller relies on external 1.1-V core (VDD), 1.8-V I/O (VCC_INTF/VCC_FLSH), and PLL reference clock (PLL_REFCLK_I) supplies, with internal power sequencing managed in coordination with DLPA200x PMICs.

Key Specifications

Pinout & Package

DLPC3420ZVB is housed in a 176-pin NFBGA package with 7.00 mm × 7.00 mm body size and 0.5-mm pitch, optimized for high-density portable display modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar display controller applications.

Compared with DLPC3430ZVB and DLPC3435ZVB, the DLPC3420ZVB provides the most balanced feature set for QnHD pico projection-retaining parallel/BT656 compatibility, CAIC, and eDRAM while minimizing BOM complexity and cost for entry-level mobile and wearable displays.

Availability

DLPC3420ZVB is available at Aetrix Electronics and suitable for mobile projector, smart display, and augmented reality glasses applications requiring stable component supply, long-term lifecycle support, and TI-qualified production-grade silicon.

Supply support for DLPC3420ZVB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and digital signal processing technologies, with leadership in DLP® display solutions since 1996.

The DLPC3420ZVB belongs to TI's DLP® Pico™ display controller product line, engineered specifically for ultra-compact, low-power projection systems using DLP160AP-class micromirror arrays in consumer and industrial wearables.

FAQ

What is the primary function of the DLPC3420ZVB in a DLP-based display system?

The DLPC3420ZVB serves as the dedicated display controller for the DLP160AP 0.16-inch QnHD DMD, translating incoming video data (via parallel, BT656, or MIPI DSI) into precisely timed sub-LVDS signals that drive the micromirror array. It performs real-time image processing-including CAIC, 1D keystone correction, and degamma-and manages DMD initialization, parking, and power sequencing in coordination with DLPA200x PMICs. This makes DLPC3420ZVB essential for enabling compact, battery-efficient pico projection.

Does the DLPC3420ZVB require an external oscillator or can it use a crystal?

The DLPC3420ZVB supports both configurations: it accepts a 27-MHz fundamental-mode crystal connected between PLL_REFCLK_I (H1) and PLL_REFCLK_O (J1), or an external 27-MHz CMOS oscillator applied solely to PLL_REFCLK_I with PLL_REFCLK_O left floating. The crystal option requires load capacitors per TI's layout guidelines; the oscillator bypasses crystal drive circuitry but must meet jitter and stability specs outlined in Section 6.10 of the DLPC3420ZVB datasheet.

How many MIPI DSI lanes does the DLPC3420ZVB support, and how is lane count configured?

The DLPC3420ZVB supports 1 to 4 MIPI DSI lanes, with DD0P/DD0N as the mandatory first lane and DD1–DD3 pairs optional based on bandwidth needs. Lane count is configured at boot via GPIO_01 and GPIO_02 pin states (per Table 5-8): 00 = 1 lane, 01 = 2 lanes, 10 = 3 lanes, 11 = 4 lanes. These pins are sampled once during power-up and then repurposed as SPI1 signals, so external pullup/pulldown resistors must remain stable during initialization.

Can the DLPC3420ZVB operate without external SDRAM?

Yes-the DLPC3420ZVB integrates embedded DRAM (eDRAM) sufficient for full-frame buffering of QnHD (320×240) video at 60 Hz, eliminating the need for external SDRAM. This reduces PCB area, BOM cost, and power consumption while simplifying layout. External flash (connected via SPI0) stores firmware and configuration data, but no external frame memory is required for basic operation with the DLP160AP DMD.

What is the role of the PARKZ signal, and how should it be driven?

PARKZ is an active-low input that triggers immediate DMD mirror parking when power loss is imminent. It must be driven low by the DLPA200x PMIC's interrupt output (not the host processor) to ensure deterministic timing and prevent partial parking that could damage the DMD. TI specifies PARKZ assertion only when normal park via GPIO_08 is not feasible-e.g., during sudden brownout-because fast park may reduce DMD lifetime if used routinely. The DLPC3420ZVB monitors PARKZ independently of RESETZ and initiates parking within microseconds.