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Texas Instruments DLPC3432CZVB
- Part No.:
- DLPC3432CZVB
- Manufacturer:
- Texas Instruments
- Category:
- Display Drivers
- Package:
- 176-VFBGA
- Datasheet:
-
DLPC3432CZVB.pdf
- Description:
- IC DRVR DLP DMD ANALOG 176NFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:260
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Product details
Overview
DLPC3432CZVB from Texas Instruments is a digital display controller IC designed specifically to drive the DLP230GP (.23 qHD) digital micromirror device (DMD). It supports up to qHD input resolution, 240-Hz frame rates, and integrates embedded frame memory (eDRAM), MIPI DSI Type 3 interface (up to 4 lanes at 470 Mbps/lane), and parallel/BT656 pixel interfaces with 155-MHz pixel clock capability.
For engineers reviewing the DLPC3432CZVB datasheet, DLPC3432CZVB pinout, DLPC3432CZVB application, or DLPC3432CZVB equivalent, key selection criteria include DMD sub-LVDS timing compliance, CAIC/IntelliBright™ image processing support, I²C-controlled LED current management, and compatibility with DLPA2000/DLPA2005/DLPA3000 PMICs for pico projector power delivery.
Technical Context
The DLPC3432CZVB implements a dedicated DMD interface with dual-mode sub-LVDS signaling (high-speed and low-speed) for mirror control, plus programmable degamma, color space conversion, 4:2:2 to 4:4:4 chroma interpolation, and 1D keystone correction. Its internal PLL supports system clock generation for synchronized DMD addressing and pixel data streaming.
It features dual I²C controllers (IIC0/IIC1) for peripheral coordination, SPI flash interface for firmware storage (up to 128 Mb), and GPIO-controlled projection enable (PROJ_ON), fast park (PARKZ), and host interrupt (HOST_IRQ) signaling - all operating at 1.8 V I/O voltage with high-voltage-tolerant I²C buffers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Resolution | Up to qHD (960 × 540); enables compact optical engine designs for sub-0.3-inch DMDs. |
| Max Frame Rate | 240 Hz; supports high-refresh-rate AR glasses and motion-sensitive pico projection. |
| Pixel Interface | 24-bit parallel or BT656; allows direct connection to mobile SoCs without external video processors. |
| MIPI DSI Support | Type 3, 1–4 lanes, 470 Mbps/lane; delivers sufficient bandwidth for qHD@120 Hz over minimal PCB routing. |
| eDRAM Size | Embedded frame buffer; eliminates need for external SDRAM in cost- and space-constrained designs. |
| DMD Interface | Sub-LVDS with training; ensures reliable high-speed mirror actuation with controlled signal integrity. |
| Flash Support | SPI interface, up to 128 Mb; stores full firmware, calibration data, and splash screen assets onboard. |
Pinout & Package
The DLPC3432CZVB is housed in a 176-pin NFBGA package with 7.00 mm × 7.00 mm body size and 0.5-mm pitch. Pin functions are defined per TI DLPS108D datasheet Rev D (October 2020), including dedicated DMD sub-LVDS differential pairs, MIPI DSI differential lanes, parallel pixel bus (24-bit), I²C, SPI, GPIO, and power domains (VDD, VCC_INTF, VCC_FLSH, VDDLP12).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PDATA_0–PDATA_23 | Parallel pixel data inputs (RGB 888) | 24-bit wide synchronous interface supporting direct RGB video input without format conversion. |
| DCLKP/DCLKN, DD0P/DD0N–DD3P/DD3N | MIPI DSI differential clock and data lanes | LVDS signaling compliant with MIPI DSI v1.3 Type 3; lane count scalable from 1 to 4 based on bandwidth needs. |
| DMD_HS_WDATAA_P/N–DMD_HS_WDATAH_P/N | DMD high-speed sub-LVDS write data | Drives DLP230GP mirror array at >100 MHz; requires matched trace lengths and series termination per TI layout guidelines. |
| DMD_LS_RDATA/DMD_LS_CLK | DMD low-speed sub-LVDS control interface | Configures DMD bias, reset, and parking states; operates at lower frequency for robust initialization and fault recovery. |
| IIC0_SDA/IIC0_SCL | Primary I²C interface | Controls DLPA200x/3000 PMICs and external peripherals; supports 1.8-V operation with high-voltage-tolerant buffers. |
| PARKZ, RESETZ, HOST_IRQ | System control signals | Active-low PARKZ triggers fast DMD mirror parking (<20 ms); RESETZ initiates full controller boot; HOST_IRQ signals frame sync or error events. |
Key Features
| Feature | Design Value |
|---|---|
| IntelliBright™ Image Processing | Real-time pixel-level luminance optimization using LABB and CAIC algorithms to extend battery life and improve perceived brightness in portable projectors. |
| Content Adaptive Illumination Control (CAIC) | Dynamically adjusts LED current per frame based on scene content, reducing thermal load and enabling smaller heat sinks in pico form factors. |
| Local Area Brightness Boost (LABB) | Enhances contrast in dark regions without clipping highlights, improving readability of text and UI elements in smart displays and AR glasses. |
| 1D Keystone Correction | Compensates for trapezoidal distortion caused by off-axis projection angles - critical for embedded projector modules with fixed lens placement. |
| Programmable Splash Screens | Displays pre-stored images from SPI flash during boot or standby, eliminating need for host processor involvement in power-up sequence. |
Applications
| Mobile Projector | Smart Display |
|---|---|
Use Scenario: Embedded pico projector in smartphone or tablet chassis projecting 720p content onto surfaces within 50 cm. IC Role / Device Role / Timing Role: Primary display controller managing DMD timing, LED current modulation, and frame buffering to maintain stable output under variable SoC bandwidth and battery voltage. Use Value: Enables <100-mW average LED power consumption via CAIC while sustaining 200-nit brightness through LABB-enhanced local contrast. | Use Scenario: Wall-mounted smart home display with integrated projector for interactive menus and ambient lighting visualization. IC Role / Device Role / Timing Role: System-on-module display controller handling HDMI-to-DMD conversion, touch feedback synchronization, and programmable LED dimming profiles. Use Value: Reduces BOM count by integrating eDRAM, degamma LUT, and color space conversion - eliminating external video processors and frame buffers. |
| Augmented Reality Glasses | Pico Projector Module |
Use Scenario: Binocular waveguide-based AR headset requiring low-latency, high-frame-rate projection with minimal thermal footprint. IC Role / Device Role / Timing Role: Real-time image processor and DMD sequencer delivering 240-Hz stereo frames with sub-1-ms latency between host GPU output and mirror actuation. Use Value: Achieves motion-to-photon latency <12 ms using hardware-accelerated 1D keystone and pixel rescaling - essential for minimizing VR sickness. | Use Scenario: OEM production of standalone pocket-sized projectors with auto-focus, tilt compensation, and wireless casting support. IC Role / Device Role / Timing Role: Central controller coordinating DMD, DLPA3000 PMIC, flash firmware, and host MCU via I²C/SPI - enabling single-chip system integration. Use Value: Supports factory-programmable calibration data and dynamic gamma curves stored in SPI flash, enabling post-manufacturing tuning without hardware revision. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar display controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DLPC3430CZVB | Same package and pinout; lacks CAIC, LABB, and IntelliBright™ suite; supports only up to 120-Hz frame rate. | Targeted at cost-sensitive, non-battery-powered smart displays where advanced image processing is unnecessary. | Select DLPC3430CZVB only if qHD@120 Hz and basic DMD control suffice - not for portable or AR use cases requiring dynamic illumination control. |
| DLPC3435CZVB | Pin-compatible upgrade; adds support for DLP230NP DMD (0.23-inch WVGA), higher DSI lane speed (500 Mbps), and enhanced thermal management. | Required for next-gen optical engines using newer DMD variants and demanding thermal envelopes in enclosed projector housings. | Choose DLPC3435CZVB when migrating to DLP230NP or requiring extended DSI bandwidth beyond 470 Mbps/lane for future-proofing. |
Compared with DLPC3430CZVB, the DLPC3432CZVB delivers 100% higher frame rate headroom and real-time illumination adaptation critical for battery-powered devices; versus DLPC3435CZVB, it offers proven qualification for DLP230GP with lower firmware complexity and mature optical module ecosystem support.
Availability
DLPC3432CZVB is available at Aetrix Electronics and suitable for mobile projector, smart display, augmented reality glasses, pico projector module, and embedded optical engine applications requiring stable component supply, long-term lifecycle assurance, and TI-qualified DLP chipset compatibility.
Supply support for DLPC3432CZVB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and digital signal processing technologies with over 90 years of innovation in power management and signal chain solutions.
The DLPC3432CZVB belongs to TI's DLP® Pico™ display controller product line, engineered specifically for ultra-compact, low-power projection systems using DLP micromirror technology - targeting consumer electronics, wearable optics, and embedded visual interfaces.
FAQ
What is the primary function of the DLPC3432CZVB in a DLP-based optical system?
The DLPC3432CZVB serves as the core display controller IC that manages all aspects of driving the DLP230GP DMD, including pixel data formatting, timing generation, image processing (IntelliBright™, CAIC, LABB), DMD interface signaling (sub-LVDS), and system coordination with PMICs like DLPA2000. It enables complete qHD projection functionality in a single chip without external frame buffers or video processors. The DLPC3432CZVB integrates eDRAM, MIPI DSI, and parallel interfaces to simplify host SoC integration.
Does the DLPC3432CZVB support both MIPI DSI and parallel pixel interfaces simultaneously?
No - the DLPC3432CZVB supports either MIPI DSI or parallel/BT656 pixel input, but not both concurrently. The interface mode is selected at boot via configuration pins or firmware initialization; mixing protocols is not supported. The DLPC3432CZVB uses dedicated physical pins for each interface (e.g., DD0P/DD0N for DSI, PDATA_0–23 for parallel), and internal routing is mutually exclusive. Designers must choose one input path based on host processor capabilities and system bandwidth requirements.
What is the role of the PARKZ signal on the DLPC3432CZVB, and how is it timed?
The PARKZ signal is an active-low DMD fast-park control input that commands immediate mechanical parking of the DLP230GP micromirrors when power loss is imminent. Per TI DLPS108D Rev D, PARKZ assertion initiates parking within 20 ms, preserving DMD longevity during unexpected shutdowns. It is typically driven by the DLPA200x/3000 PMIC's interrupt output and must be asserted before VDD drops below operational threshold. The DLPC3432CZVB monitors PARKZ independently of RESETZ and halts DMD addressing upon detection.
Can the DLPC3432CZVB operate without external SPI flash memory?
Yes - the DLPC3432CZVB can operate without external SPI flash, but only in limited configurations. Firmware and calibration data must be loaded externally via I²C or parallel interface during initialization; however, features dependent on flash - such as programmable splash screens, persistent gamma tables, and factory calibration storage - become unavailable. TI recommends SPI flash (up to 128 Mb) for production systems to ensure robust boot, field-upgradable firmware, and consistent image quality across units. The DLPC3432CZVB includes internal ROM for minimal bootloader execution.
How does the DLPC3432CZVB handle color space conversion and degamma correction?
The DLPC3432CZVB performs hardware-accelerated color space conversion (e.g., RGB to YCbCr) and programmable degamma correction using on-chip LUTs and processing pipelines. Degamma tables are configurable via I²C or loaded from SPI flash, supporting multiple curves for different display surfaces or ambient conditions. Color space conversion is applied prior to DMD loading and supports standard ITU-R BT.601/709 matrices. These functions execute in real time without CPU intervention, ensuring deterministic latency - a requirement confirmed in TI's DLPS108D Section 7.3.4 for the DLPC3432CZVB.
DLPC3432CZVB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 176-VFBGA
- Packaging:
- Tray
- Product Status:
- Active
- Display Type:
- DLP
- Configuration:
- -
- Interface:
- I2C
- Digits or Characters:
- -
- Current - Supply:
- -
- Voltage - Supply:
- 1.045V ~ 1.155V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 176-NFBGA (7x7)
DLPC3432CZVB FAQ
1.How can I place an order for DLPC3432CZVB through Aetrix?
Please submit a Request for Quotation (RFQ) for DLPC3432CZVB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DLPC3432CZVB reliable?
The price and inventory of DLPC3432CZVB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DLPC3432CZVB is usually 5 days.
3.What payment methods are accepted for DLPC3432CZVB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DLPC3432CZVB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DLPC3432CZVB?
DLPC3432CZVB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DLPC3432CZVB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DLPC3432CZVB?
For technical support, including DLPC3432CZVB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DLPC3432CZVB requirements.
6.How does Aetrix verify that DLPC3432CZVB is sourced from the original manufacturer or authorized distributors?
All DLPC3432CZVB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DLPC3432CZVB meets industry standards.
7.What is the process for return or replacement of DLPC3432CZVB?
All DLPC3432CZVB units undergo pre-shipment inspection (PSI). If there is an issue with DLPC3432CZVB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DLPC3432CZVB part is unused and in its original packaging.
Return procedure for DLPC3432CZVB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DLPC3432CZVB Tags
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