Texas Instruments DLPC900AZPC
- Part No.:
- DLPC900AZPC
- Manufacturer:
- Texas Instruments
- Category:
- Display Drivers
- Package:
- 516-BGA
- Datasheet:
-
DLPC900AZPC.pdf
- Description:
- IC DMD CONTROLLER 516BGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,228
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DLPC900AZPC from Texas Instruments is a high-performance digital micromirror device (DMD) controller supporting DLP500YX, DLP5500, DLP6500, DLP670S, and DLP9000 DMDs for industrial light control. It delivers programmable pattern rates up to 16.1 kHz (1-bit pre-stored mode), integrates 128 MB internal DRAM, and supports dual 24-bit RGB video inputs up to 120 Hz for WQXGA resolution.
For engineers reviewing the DLPC900AZPC datasheet, DLPC900AZPC pinout, DLPC900AZPC application, or DLPC900AZPC equivalent, this controller enables precise synchronization with cameras/sensors via two configurable triggers, offers USB 1.1 and three I²C interfaces, and provides fully programmable GPIO/PWM for adaptive lighting and 3D scanning system integration.
Technical Context
The DLPC900AZPC implements a scalable architecture with dual pixel input ports (Port 1 and Port 2), each supporting 24-bit RGB/YUV data at up to 120 Hz, and configurable as independent 24-bit ports or combined 48-bit interface for two-pixel-per-clock operation. Its DMD interface uses dual-channel LVDS (A and B), each with 16-bit differential serial data lanes, dedicated differential clocks (DCKA_P/N, DCKB_P/N), and serial control (SCA_P/N, SCB_P/N).
It integrates a system oscillator input (MOSC) with 25 ms stabilization requirement post-POSENSE, programmable output clock OCLKA (default 787 kHz), and three JTAG debug interfaces (TCK/TDI/TDO1 for boundary scan; TMS2/TDO2/RTCK for ICE). Power sequencing relies on POSENSE and PWRGOOD signals with hysteresis, driving three active-low reset outputs (EXT_ARSTZ, CTRL_ARSTZ, AFE_ARSTZ) with ≥2 ms assertion time.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Pattern Rate | Up to 16129 Hz in 1-bit pre-stored mode for DLP500YX - enables sub-millisecond exposure in high-speed 3D scanning. |
| Internal Memory | 128 MB DRAM - buffers 400–1024 1-bit patterns depending on DMD resolution, eliminating external frame buffer design. |
| Video Input | Dual 24-bit RGB up to 120 Hz, supporting WQXGA (DLP9000), 2048×1200 (DLP500YX), and 2716×1600 (DLP670S) - requires two DLPC900AZPC controllers for highest-resolution DMDs. |
| DMD Interface | Dual LVDS channels (A/B), each with 16-bit differential data, dedicated clock, and serial control - ensures noise-immune, high-bandwidth DMD drive for industrial-grade reliability. |
| Control Interfaces | One USB 1.1 target port + three I²C ports + LED enable/PWM generators - supports host PC configuration, sensor communication, and illumination modulation without external logic. |
| Package | 516-pin BGA, 27.00 mm × 27.00 mm - compatible with standard industrial PCB assembly processes and thermal management requirements. |
Pinout & Package
DLPC900AZPC is housed in a 516-pin ZPC package (BGA), measuring 27.00 mm × 27.00 mm, with 0.8 mm ball pitch and RoHS-compliant finish. Thermal pad exposed on underside for enhanced heat dissipation in continuous high-throughput operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| POSENSE (P22) | Power-on sense input | Active-high signal with hysteresis indicating all supplies have reached ≥90% of min spec - initiates controlled firmware boot sequence. |
| PWRGOOD (T26) | System power-good indicator | External voltage monitor output signaling safe exit from reset - required before releasing EXT_ARSTZ/CTRL_ARSTZ. |
| DADOEZ (AE7) | DMD output-enable (active low) | Enables/disables DMD data transmission - not used on secondary controller in dual-controller configurations. |
| DCKA_P/N (V4/V3) | DMD LVDS channel A clock | Differential clock pair driving LVDS serial data for DMD channel A - critical for timing-critical pattern loading. |
| P_CLK1 (AE22) | Pixel input clock (Port 1) | Selectable edge-triggered clock for 24-bit RGB/YUV pixel data ingestion - supports flexible sync with external video sources. |
Key Features
| Feature | Design Value |
|---|---|
| Scalable DMD support | Single controller drives DLP500YX, DLP5500, DLP6500; dual DLPC900AZPC required for DLP670S/DLP9000 - simplifies platform reuse across resolution tiers. |
| Camera/sensor synchronization | Two configurable input/output trigger lines - enables deterministic latency alignment between DMD pattern display and image capture in 3D machine vision. |
| Programmable illumination control | Dedicated LED enable and PWM generators - allows real-time intensity modulation synchronized to DMD patterns for structured light projection. |
| Flexible pixel interface | Dual 24-bit ports (Port 1/Port 2), reconfigurable as 48-bit interface - accommodates both standard video sources and high-throughput parallel pixel streams. |
| Robust debug infrastructure | Dual JTAG paths: Boundary Scan (TCK/TDI/TDO1) and ICE (TMS2/TDO2/RTCK) - supports production test, firmware development, and field diagnostics without hardware redesign. |
Applications
| 3D Machine Vision | 3D Printing |
|---|---|
Use Scenario: Real-time surface reconstruction of manufactured parts using structured light projection and stereo camera capture. IC Role / Device Role / Timing Role: DLPC900AZPC generates precisely timed binary patterns at >10 kHz and synchronizes DMD exposure with camera trigger signals. Use Value: Enables micron-level depth accuracy and <100 µs inter-pattern latency for high-throughput inline inspection systems. |
Use Scenario: Layer-by-layer photopolymer curing in mask-based stereolithography (SLA) printers. IC Role / Device Role / Timing Role: DLPC900AZPC drives DLP6500/DLP9000 DMDs to project UV-curable resin exposure masks with sub-pixel registration. Use Value: Supports 25–50 µm XY resolution and consistent 35–100 µm layer thickness across full build area. |
| Ophthalmology Imaging | 3D Scanning for Limb Measurement |
Use Scenario: Confocal retinal imaging and anterior segment tomography requiring adaptive illumination patterns. IC Role / Device Role / Timing Role: DLPC900AZPC executes multi-wavelength, multi-exposure sequences while modulating LED intensity via integrated PWM. Use Value: Delivers dynamic range >70 dB and temporal stability <0.5% RMS intensity variation over clinical acquisition windows. |
Use Scenario: Contactless anthropometric measurement of prosthetic limb sockets or orthopedic braces. IC Role / Device Role / Timing Role: DLPC900AZPC projects calibrated fringe patterns onto skin surfaces and coordinates with synchronized IR camera capture. Use Value: Achieves ±0.1 mm point-cloud repeatability across 300–500 mm working distance with ambient light rejection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar DMD controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DLPC350ZCE | Lower pattern rate (≤1200 Hz), 64 MB DRAM, supports only DLP4500/DLP3010 DMDs - no LVDS DMD interface. | Targeted at entry-level 3D scanning and educational kits; lacks dual-port video and illumination modulation features. | Select DLPC350ZCE only for cost-sensitive, lower-resolution applications where 16 kHz pattern rates and WQXGA video are unnecessary. |
| DLPC3478ZWT | Integrated DMD driver, 128 MB DRAM, supports DLP4710/DLP6500 - uses parallel DMD interface, not LVDS; no USB interface. | Optimized for compact embedded projectors; lacks camera trigger synchronization and programmable GPIO/PWM for external sensors. | Choose DLPC3478ZWT when board space is constrained and system-level integration favors single-chip projector engines over modular DMD+controller designs. |
Compared with DLPC350ZCE and DLPC3478ZWT, the DLPC900AZPC uniquely combines ultra-high pattern rates, dual LVDS DMD drive, and synchronized camera triggering - making it the only option for industrial 3D metrology systems requiring >10 kHz structured light projection with sub-millisecond latency control.
Availability
DLPC900AZPC is available at Aetrix Electronics and suitable for 3D machine vision, additive manufacturing, and medical imaging applications requiring stable component supply, long-term industrial lifecycle support, and traceable sourcing.
Supply support for DLPC900AZPC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and digital light control technologies, with decades of DLP® innovation in industrial, automotive, and consumer markets.
The DLPC900AZPC belongs to TI's DLP® advanced light control product line, engineered specifically for high-precision, high-speed structured light applications in industrial automation, medical diagnostics, and scientific instrumentation.
FAQ
What DMD devices does the DLPC900AZPC support?
The DLPC900AZPC supports DLP500YX, DLP5500, DLP6500, DLP670S, and DLP9000 digital micromirror devices. For DLP670S and DLP9000, two DLPC900AZPC controllers are required in tandem to manage full-resolution pattern data and timing. The controller's LVDS DMD interface and 128 MB DRAM are optimized for these high-density DMDs' bandwidth and buffering needs.
Does the DLPC900AZPC include internal memory for pattern storage?
Yes, the DLPC900AZPC integrates 128 MB of internal DRAM, sufficient to buffer between 400 and 1024 1-bit patterns depending on the connected DMD's resolution. This eliminates the need for external frame buffers in most industrial applications and reduces system latency by enabling direct pattern access from on-chip memory during high-speed projection sequences.
How does the DLPC900AZPC synchronize with external cameras or sensors?
The DLPC900AZPC provides two configurable input and output trigger lines that can be programmed for precise timing alignment with external cameras or sensors. These triggers operate with sub-microsecond jitter and support both hardware-level synchronization and software-defined delay offsets, ensuring deterministic latency between DMD pattern display and image capture in 3D scanning and machine vision systems.
What video input formats and resolutions does the DLPC900AZPC accept?
The DLPC900AZPC accepts dual 24-bit RGB, YUV, or YCrCb video inputs up to 120 Hz, supporting standard formats from XGA to WQXGA. It natively handles DLP9000 (WQXGA), DLP500YX (2048×1200), and DLP670S (2716×1600) - though the latter two require two DLPC900AZPC controllers operating in coordinated mode for full-resolution video streaming.
What interfaces are available for configuring and controlling the DLPC900AZPC?
The DLPC900AZPC offers one USB 1.1 target port for host PC configuration, three I²C ports for peripheral communication (e.g., temperature sensors, EEPROMs), and dedicated LED enable/PWM generator outputs for illumination control. These interfaces allow full system initialization, real-time parameter adjustment, and closed-loop light modulation without requiring additional microcontrollers or FPGAs.
DLPC900AZPC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 516-BGA
- Packaging:
- Tube
- Product Status:
- Active
- Display Type:
- DMD
- Configuration:
- -
- Interface:
- I2C, SPI
- Digits or Characters:
- -
- Current - Supply:
- -
- Voltage - Supply:
- 1.09V ~ 1.2V, 1.1V ~ 1.2V, 1.71V ~ 1.89V, 3.135V ~ 3.465V
- Operating Temperature:
- 0°C ~ 55°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 516-BGA (27x27)
DLPC900AZPC FAQ
1.How can I place an order for DLPC900AZPC through Aetrix?
Please submit a Request for Quotation (RFQ) for DLPC900AZPC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DLPC900AZPC reliable?
The price and inventory of DLPC900AZPC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DLPC900AZPC is usually 5 days.
3.What payment methods are accepted for DLPC900AZPC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DLPC900AZPC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DLPC900AZPC?
DLPC900AZPC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DLPC900AZPC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DLPC900AZPC?
For technical support, including DLPC900AZPC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DLPC900AZPC requirements.
6.How does Aetrix verify that DLPC900AZPC is sourced from the original manufacturer or authorized distributors?
All DLPC900AZPC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DLPC900AZPC meets industry standards.
7.What is the process for return or replacement of DLPC900AZPC?
All DLPC900AZPC units undergo pre-shipment inspection (PSI). If there is an issue with DLPC900AZPC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DLPC900AZPC part is unused and in its original packaging.
Return procedure for DLPC900AZPC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DLPC900AZPC Tags

-
PCA8561AHN/AY
NXP Semiconductors

-
SN74LS47N
Texas Instruments

-
PCF85176T/1Y
NXP Semiconductors

-
PCF85176H/1,518
NXP Semiconductors

-
BU9796AMUV-E2
Rohm Semiconductor

-
PCA85176H/Q900/1,5
NXP Semiconductors

-
PCF8537AH/1,518
NXP Semiconductors

-
LM3914VX/NOPB
Texas Instruments

-
PCF85134HL/1,118
NXP Semiconductors

-
AS1115-BSST
ams-OSRAM USA INC.

-
PCA8534AH/Q900/1,5
NXP Semiconductors

-
LM3914V/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
