Texas Instruments DM385AAAR21

Overview

DM385AAAR21 from Texas Instruments is a high-performance, low-power DaVinci™ digital media processor SoC featuring an ARM Cortex-A8 core running up to 1000 MHz, integrated HDVICP2 video coprocessor supporting real-time H.264 BP/MP/HP encode/decode at 1080p60, and dual 165-MHz HD video capture inputs. It delivers 2000 ARM Cortex-A8 MIPS and includes 256KB L2 cache with ECC, targeting IP netcams and HD video conferencing endpoints.

For engineers reviewing the DM385AAAR21 datasheet, DM385AAAR21 pinout, DM385AAAR21 application, or DM385AAAR21 equivalent, key selection criteria include its 609-pin AAR BGA package, DDR2/DDR3/DDR3L memory interface (up to 533 MHz), PCIe 2.0 x1 support, dual USB 2.0 ports with PHYs, and hardware-accelerated imaging subsystem including ISS, HDVPSS, and Face Detect engine.

Technical Context

The DM385AAAR21 implements a heterogeneous architecture where the ARM Cortex-A8 RISC processor handles system control and OS execution while offloading intensive video and imaging tasks to dedicated hardware blocks: HDVICP2 for H.264/MPEG-2/VC-1 encode/decode, ISS for camera sensor interfacing and real-time image processing (IPIPE, H3A, FD), and HDVPSS for dual HD capture/display with HDMI 1.3 transmitter and analog DACs.

Its interconnect uses a 128-bit L3 bus with DMM for efficient tiled memory access, SmartReflex™ Level 2b for dynamic voltage/frequency scaling across multiple power domains, and EDMA with 64 channels plus 8 QDMA channels to sustain high-bandwidth data movement between DDR, on-chip RAM (256KB OCMC), peripherals, and coprocessors without CPU intervention.

Key Specifications

Pinout & Package

DM385AAAR21 is housed in a 609-pin Pb-free BGA package (AAR suffix) with 0.8-mm effective pitch and Via Channel™ technology, measuring 16 × 16 mm. This package supports high I/O density required for parallel camera interfaces, DDR memory, and multiple high-speed serial peripherals while reducing PCB layer count and cost.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar digital media processor applications.

Compared with DM388AAAR21, DM385AAAR21 omits the noise filter and limits ARM frequency to 1000 MHz (no OPP100), reducing BOM cost while retaining identical video I/O, encode/decode capability, and pin compatibility. Against i.MX6Q, DM385AAAR21 delivers higher H.264 encode efficiency and lower power per stream but less general-purpose compute headroom.

Availability

DM385AAAR21 is available at Aetrix Electronics and suitable for IP network cameras, HD video conferencing endpoints, and digital signage media players requiring stable component supply and long-term industrial availability.

Supply support for DM385AAAR21 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and wireless technologies, with leadership in industrial, automotive, and consumer markets.

The DM385AAAR21 belongs to TI's DaVinci™ digital media processor product line, designed specifically for cost-sensitive, low-power HD video capture, encode, and display applications in embedded vision systems.

FAQ

What video codecs does the DM385AAAR21 hardware accelerate?

The DM385AAAR21 integrates the HDVICP2 coprocessor, which provides hardware acceleration for H.264 BP/MP/HP, MPEG-2, VC-1 SP/MP/AP, MPEG-4 ASP/SP, MJPEG, and JPEG encode/decode operations. It supports real-time 1080p60 encoding and decoding, enabling efficient use of system resources and reduced thermal load compared to software-only implementations. The DM385AAAR21 does not support AV1 or VP9 in hardware.

Does the DM385AAAR21 support PCIe Gen2, and what configuration options are available?

Yes, the DM385AAAR21 includes a PCI Express 2.0 port compliant with Gen2 (5.0 GT/s) and configurable as either Root Complex or Endpoint mode. It supports a single lane (x1) topology and is enabled on all DM385 devices. The DM385AAAR21 uses this interface for high-speed expansion-such as connecting FPGA co-processors or NVMe storage controllers-without consuming bandwidth from the DDR or EMAC interfaces.

What is the maximum DDR memory speed supported by the DM385AAAR21?

The DM385AAAR21 supports DDR2 up to 400 MHz, DDR3 up to 533 MHz, and DDR3L up to 533 MHz. Its 32-bit DDR interface allows up to 2GB total address space across up to two x16 devices. The memory controller includes features like DMM for efficient tiled access and ECC support on L2 cache, but DDR itself does not include built-in ECC-external DDR chips must be selected accordingly.

How many camera sensors can the DM385AAAR21 interface simultaneously?

The DM385AAAR21 supports up to two independent HD camera inputs concurrently: two 165-MHz HD video capture ports, or one HD port plus split SD ports (dual 8-bit). It also includes a parallel raw interface (up to 16-bit) and CSI2 serial interface for additional sensors. The Imaging Subsystem (ISS) processes all inputs through shared hardware blocks (IPIPE, H3A, FD), enabling synchronized multi-sensor operation in applications like stereo vision or panoramic stitching.

Is the DM385AAAR21 pin-compatible with the DM388AAAR21?

Yes, the DM385AAAR21 and DM388AAAR21 share identical 609-pin AAR BGA packaging, pin assignments, and electrical characteristics. They differ only in internal silicon features: DM388AAAR21 adds the fourth-generation motion-compensated noise filter and supports OPP100 (600 MHz ARM), while DM385AAAR21 does not. This allows drop-in replacement in most designs where noise filtering is not required, simplifying migration paths and inventory management.