Diodes Incorporated DML1009LDS-7

Overview

DML1009LDS from Diodes Incorporated is a single-channel smart load switch featuring an N-channel MOSFET with 5 mΩ R_DS(ON) at V_BIAS = 5 V and V_IN = 1.05 V, 10 A continuous current capability, 3.2–5.5 V bias supply range, and integrated quick output discharge. It enables power sequencing in portable computing and SSD applications where low-loss, fast switching, and compact footprint are critical.

For engineers reviewing the DML1009LDS datasheet, DML1009LDS pinout, DML1009LDS application, or DML1009LDS equivalent, key selection criteria include input voltage compatibility (0.8 V to V_BIAS−1.5 V), quiescent current (35 µA), turn-on rise time (5 µs typ.), thermal resistance (θ_JA = 60 °C/W), and V-DFN3030-8 package integration for high-density PCB layouts.

Technical Context

The DML1009LDS implements a logic-controlled N-channel MOSFET load switch with internal gate drive optimized for low-V_IN operation down to 0.8 V while maintaining stable R_DS(ON) across 3.2–5.5 V V_BIAS. Its ON pin accepts TTL/CMOS-compatible control (V_ONH ≥ 1.2 V, V_ONL ≤ 0.5 V) and drives the FET directly without external components.

It integrates a 200 Ω pull-down resistor on the OUT pin for controlled discharge when disabled, eliminating need for external circuitry. Thermal design relies on the exposed EPAD (Pin 2) and θ_JC = 8 °C/W to sustain 10 A continuous current under ambient ≤ +85 °C with proper PCB copper area.

Key Specifications

Pinout & Package

V-DFN3030-8 (Type R) package with 3.0 mm × 3.0 mm body, 0.8 mm height, and exposed thermal pad (EPAD) on Pin 2 for enhanced heat dissipation. RoHS-compliant, halogen-free, moisture sensitivity level 1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar load switch applications.

Compared with TPS22965DSGR and RT9711CGQW, DML1009LDS delivers superior combination of ultra-low R_DS(ON), 10 A capacity, integrated discharge, and sub-10 µs switching-making it optimal for high-density, high-efficiency portable computing power domains.

Availability

DML1009LDS is available at Aetrix Electronics and suitable for SSD power management, ultrabook core rail sequencing, and tablet display backlight control requiring stable component supply, full traceability, and long-term lifecycle support.

Supply support for DML1009LDS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-performance, energy-efficient solutions for computing, consumer, and industrial markets.

The DML1009LDS belongs to Diodes' Smart Load Switch product line, engineered specifically for low-voltage, high-current power gating in space-constrained portable electronics with emphasis on thermal efficiency and integration.

FAQ

What is the minimum recommended input voltage for reliable operation?

The DML1009LDS supports input voltages as low as 0.8 V when V_BIAS ≥ 3.2 V. However, for guaranteed R_DS(ON) ≤ 5 mΩ, V_IN must be ≤ V_BIAS − 1.5 V (e.g., V_IN ≤ 3.5 V when V_BIAS = 5 V). Operation below 0.8 V may result in undefined behavior or increased R_DS(ON).

Can the ON pin be driven directly from a 1.8 V GPIO without level shifting?

Yes. The ON pin has TTL/CMOS-compatible thresholds: V_ONH ≥ 1.2 V (min) and V_ONL ≤ 0.5 V (max). A 1.8 V GPIO satisfies the high-level requirement with 0.6 V noise margin and remains safely above V_ONL, enabling direct interface without external level translation.

How does the integrated output discharge resistor affect system timing?

The 200 Ω internal pull-down discharges a 100 nF output capacitor in approximately 20 µs (τ = R × C). This ensures rapid, predictable discharge after disable-critical for preventing latch-up in downstream logic and meeting USB or PCIe reset timing requirements without adding external components.

Is thermal derating required for 10 A operation in a standard 4-layer PCB?

At 10 A continuous, junction temperature rise depends on PCB copper area. With 1 in² of 2 oz Cu connected to the EPAD, θ_JA ≈ 60 °C/W yields ~60 °C rise at +25 °C ambient-well below the 150 °C limit. For sustained 10 A, ensure ≥1 in² thermal pad area and avoid enclosing the device in sealed enclosures without airflow.