Texas Instruments DP83815DVNG

Overview

DP83815DVNG from National Semiconductor is a single-chip 10/100 Mb/s PCI Ethernet MAC+PHY (MacPhyter™) with integrated 3.3V CMOS physical layer, 2 KB Tx/Rx FIFOs, IEEE 802.3/802.3u compliance, and Wake-on-LAN support. It targets low-cost PC motherboards, adapter cards, and embedded systems requiring full-duplex operation, VLAN support, and MII interface for external PHY extension.

For engineers reviewing the DP83815DVNG datasheet, DP83815DVNG pinout, DP83815DVNG application, or DP83815DVNG equivalent, key selection considerations include its 144-pin LQFP (VNG) package, PCI V2.2 bus mastering up to 128-dword bursts, auto-negotiation via EEPROM configuration, and hardware-accelerated Rx packet filtering with 512-entry hash table and deep pattern matching.

Technical Context

The DP83815DVNG integrates an enhanced National Semiconductor PCI MAC/BIU with a fully compliant 3.3V CMOS PHY supporting both 10BASE-T and 100BASE-TX. Its MAC implements IEEE 802.3x flow control, RFC 1213/1398 MIB statistics, and flexible descriptor-based DMA with bus-mastering transfers.

PHY functionality includes adaptive equalization, baseline wander compensation, MLT-3 encoding/decoding, 4B/5B conversion, and full auto-negotiation per IEEE 802.3u. The device supports Clkrun, PME, and multiple power states (D0–D3cold), with WOL wake events including Magic Packet™, directed packets, ARP, VLAN, and PHY status change.

Key Specifications

Pinout & Package

DP83815DVNG is housed in a 144-pin LQFP package (NS package code VNG144A), with 3.3V I/O and core supply rails, dedicated PCI bus interface pins (AD[31:0], CBEN[3:0], PCICLK, FRAMEN, etc.), integrated PHY I/O (TPTDP/TPTDM, TPRDP/TPRDM), MII interface (RXD[3:0], TXD[3:0], CRS, COL, MDIO/MDC), and power management signals (PMEN/CLKRUNN, PWRGOOD, 3VAUX).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Ethernet controller applications.

Compared with RTL8139D-GR and Intel 82559ER, DP83815DVNG uniquely delivers integrated PHY, hardware-accelerated 4-pattern WOL filtering, and PCI V2.2 bus mastering in a 144-pin LQFP - making it optimal for cost-sensitive, space-constrained designs needing full feature parity without external components.

Availability

DP83815DVNG is available at Aetrix Electronics and suitable for PC motherboard integration, industrial embedded networking, low-cost adapter cards, and Wake-on-LAN enabled systems requiring stable component supply and long-term obsolescence planning.

Supply support for DP83815DVNG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

National Semiconductor was a U.S.-based semiconductor company specializing in analog and mixed-signal ICs, acquired by Texas Instruments in 2011. It pioneered integrated Ethernet solutions for PC and embedded markets.

The DP83815DVNG belongs to National's MacPhyter™ family of integrated MAC+PHY controllers, designed specifically to reduce BOM cost and design complexity in volume PC and embedded Ethernet applications.

FAQ

What is the package type and pin count of the DP83815DVNG?

The DP83815DVNG uses a 144-pin LQFP package (National Semiconductor package code VNG144A). This is confirmed in the official datasheet Section 1.1 "144 LQFP Package (VNG)" and pin diagram on page 4. It is distinct from the 160-pin LBGA variant (DP83815DUJB) and shares no pin compatibility with that version. The DP83815DVNG pinout includes dedicated PCI bus signals, integrated PHY I/O, MII interface, and power management terminals.

Does the DP83815DVNG support full-duplex operation at both 10 Mb/s and 100 Mb/s?

Yes, the DP83815DVNG supports full-duplex transmission and reception at both 10 Mb/s and 100 Mb/s data rates, as explicitly stated in the General Description and Features sections of the SNLS059E datasheet. It implements IEEE 802.3x flow control to manage buffer congestion in full-duplex mode and maintains minimum interframe gap compliance for reliable operation across both speeds.

How does Wake-on-LAN functionality work on the DP83815DVNG?

The DP83815DVNG implements hardware-based Wake-on-LAN per PC98/PC99 and OnNow specifications. It monitors the network link for Magic Packet™, directed packets, ARP requests, VLAN-tagged frames, configurable pattern matches, and PHY status changes - all while operating in low-power WOL mode (380 mW). Wake events trigger assertion of the PMEN signal, allowing the system to exit sleep state without host CPU involvement.

Can the DP83815DVNG interface with an external PHY using the MII?

Yes, the DP83815DVNG provides a complete Media Independent Interface (MII) with RXD[3:0], TXD[3:0], CRS, COL, RXDV, RXER, TXEN, TXCLK, MDIO, and MDC signals. When the CFG:EXT_PHY bit is set, the internal PHY is disabled and MII signals become active - enabling connection to external 10/100 or 1000BASE-X PHYs per IEEE 802.3 Clause 22.

What power supply requirements does the DP83815DVNG have?

The DP83815DVNG requires a single 3.3V supply for I/O and core logic, with separate analog voltage domains (PHYVDD1/2, RXAVDD1/2, TXDVDD) and dedicated ground planes (SUBGND1/2/3, MACVSS1/2, PHYVSS1/2). DC specifications confirm operation at 3.3V ±0.3V, with typical active power consumption of 561 mW and strict decoupling requirements detailed in Section 7.1 of SNLS059E.