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Texas Instruments DP83907VF
- Part No.:
- DP83907VF
- Manufacturer:
- Texas Instruments
- Category:
- Controllers
- Package:
- 132-BQFP Bumpered
- Datasheet:
-
DP83907VF.pdf
- Description:
- IC CONTROLLR AT/LANII TP 132QFP
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
DP83907VF from National Semiconductor is a CMOS VLSI Ethernet Network Interface Controller integrating ISA bus interface, IEEE 802.3-compliant MAC, ENDEC, and on-chip 10BASE-T transceiver. It supports 10 Mbps Manchester encoding/decoding, AUI (10BASE5/10BASE2), and TPI (10BASE-T) interfaces, operates from a single 5V supply, and enables jumperless configuration via EEPROM or hardware pins for NE2000-compatible PC AT systems.
For engineers reviewing the DP83907VF datasheet, DP83907VF pinout, DP83907VF application, or DP83907VF equivalent, key selection considerations include ISA bus compatibility (8-/16-bit mode detection via MSA9), integrated transceiver compliance with IEEE 802.3 Clause 14, EEPROM-based configuration storage (NMC93C06), activity/collision/link-integrity LED drive capability, and dual-media support (AUI + TPI) without external bus logic.
Technical Context
The DP83907VF implements a full OSI Layer 2 solution: its MAC module provides packet transmission/reception control via off-board memory accessed through I/O ports; the ENDEC module performs 10 Mbit/s Manchester encode/decode with squelch on receive/collision pairs and phase-locked loop decoding; the integrated 10BASE-T transceiver includes collision detect, heartbeat, jabber, link integrity test, polarity correction, and auto-switch functionality.
Its ISA bus interface supports NE2000 Architecture–compatible I/O mapping (base address configurable via Configuration Register A), remote DMA transfers between internal buffer RAM and host system, and automatic 8-/16-bit slot detection using MSA9 pull-up/pull-down behavior. Power-on reset requires ≥415 ms assertion to load configuration registers and initiate EEPROM PROM space loading.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | 10 Mbps - Fixed-rate Ethernet operation per IEEE 802.3 standard. |
| Encoding | Manchester - Ensures DC balance and clock recovery in baseband signaling. |
| Supply Voltage | Single 5V - Powers core logic, analog PHY circuitry (AVCC/XVCC/TPVCC), and drivers without auxiliary rails. |
| Bus Interface | ISA (8-/16-bit) - Fully compatible with Industry Standard Architecture slots; mode auto-detected at reset via MSA9. |
| Media Support | AUI + 10BASE-T - Dual-interface capability: differential AUI port for 10BASE5/10BASE2 and integrated TPI transceiver for twisted-pair. |
| EEPROM Interface | NMC93C06-compatible serial - Enables in-situ programming of Ethernet MAC address, configuration registers, and boot data. |
| Interrupt Lines | IRQ3/4/5/9/10/11/12/15 - Software-selectable via Configuration Register A for flexible system integration. |
Pinout & Package
DP83907VF is housed in a 132-pin LQFP package (NS package code VF132A), with dedicated ISA bus interface pins, dual-media network I/O (AUI and TPI), EEPROM control signals, and segregated power domains (coreVCC/GND, AVCC/AGND, TPVCC/TPGND, XVCC/XGND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SA0–SA9 | Latched Address Bus (Low) | Decodes DP83907VF I/O map accesses; 10-bit subset of 20-bit ISA address bus. |
| SD0–SD15 | System Data Bus | 16-bit bidirectional path for register and buffer memory transfers; supports both 8- and 16-bit ISA modes. |
| IORD / IOWR | I/O Read/Write Strobes | TTL-compatible control signals initiating register reads/writes within configured I/O port address space. |
| TXOda, TXOb, TXOa, TXOdb | TPI Transmit Outputs | High-drive CMOS differential outputs resistively combined externally for ISI-compensated 10BASE-T signaling. |
| RXIa, RXIb | TPI Receive Inputs | Differential inputs feeding ENDEC amplifier; enable direct connection to twisted-pair media via pulse transformer. |
| ACT_led, COL_led, GDLNK_led | LED Drive Outputs | Open-drain active-low signals indicating packet activity (≈50 ms pulse), collision detection, and verified 10BASE-T link integrity. |
| MSD0–MSD7, CA0–CA7, DO/DI/SK | EEPROM Interface | Serial interface (DO/DI/SK) and parallel configuration input (MSD/CA) for loading Configuration Registers A/B/C and Ethernet address at reset. |
| RESET | Power-On Reset Input | Must be asserted ≥415 ms to trigger internal RegLoad signal and initiate EEPROM PROM loading sequence. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 10BASE-T Transceiver | Fully complies with IEEE 802.3 Clause 14: includes collision detect, heartbeat, jabber, link integrity test, polarity correction, and on-chip filtering - eliminates need for external PHY IC. |
| NE2000 Software Compatibility | Registers and I/O port layout match Novell's NE2000 Architecture, enabling use of standard DOS/Windows drivers without modification. |
| Jumperless Configuration | Configuration Register A mapped to I/O address 278H (printer port data register); four consecutive writes enable runtime I/O base address reprogramming. |
| EEPROM-Based Non-Volatile Storage | Stores MAC address, configuration bits (A/B/C), and signature data in external NMC93C06; supports in-circuit programming during production or field update. |
| Dual-Media Interface Support | Simultaneous AUI (10BASE5/10BASE2) and TPI (10BASE-T) connectivity - selectable via Configuration Register B; THIN output enables DC-DC converter for thin coaxial operation. |
Applications
| Industrial PC Networking | Legacy ISA-Based Embedded Systems |
|---|---|
|
Use Scenario: Retrofitting Ethernet connectivity into aging industrial control cabinets using ISA backplanes and DOS-based HMI software. IC Role / Device Role / Timing Role: DP83907VF serves as the complete MAC-PHY layer, handling packet framing, Manchester encoding/decoding, and physical layer signaling over 10BASE-T or AUI. Use Value: Eliminates need for discrete transceivers and bus glue logic, reducing BOM count and PCB area while maintaining NE2000 driver compatibility for zero-software-change deployment. |
Use Scenario: Adding wired Ethernet to custom ISA expansion cards for medical instrumentation requiring deterministic real-time packet handling. IC Role / Device Role / Timing Role: DP83907VF acts as the network interface controller with remote DMA access to local SRAM buffers, enabling low-latency packet transfer without CPU intervention. Use Value: Integrated CHRDY wait-state generation ensures reliable timing alignment with legacy ISA bus cycles, preventing data corruption during high-throughput transfers. |
| PC AT-Compatible Network Adapters | Thin Ethernet (10BASE2) Node Controllers |
|
Use Scenario: Manufacturing cost-optimized NE2000-compatible Ethernet cards for retrocomputing and educational platforms. IC Role / Device Role / Timing Role: DP83907VF functions as the central controller, providing ISA bus arbitration, interrupt management (IRQ3–15), and LED status indication (ACT/COL/GDLNK). Use Value: Single-chip integration reduces component count by >12 devices versus discrete DP8390 + external transceiver designs, lowering assembly cost and improving yield. |
Use Scenario: Deploying endpoint nodes in daisy-chained thin coaxial networks for factory-floor sensor aggregation. IC Role / Device Role / Timing Role: DP83907VF configures its THIN output to enable an external DC-DC converter, powering the 10BASE2 transceiver while maintaining AUI isolation requirements. Use Value: Hardware-selectable cabling mode (via Configuration Register B) allows one PCB design to support both 10BASE2 and 10BASE-T deployments without layout changes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Ethernet controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| RTL8019AS | PCI bus interface (not ISA); lacks integrated 10BASE-T transceiver - requires external PHY or AUI-only operation. | Targets newer x86 systems with PCI slots; not drop-in replaceable in ISA-based designs. | Choose RTL8019AS only when migrating from ISA to PCI infrastructure and external PHY integration is acceptable. |
| DM9009 | 3.3V core logic with 5V-tolerant I/O; supports both ISA and LPC interfaces; no integrated 10BASE-T transceiver. | Designed for low-power embedded x86 platforms; requires external magnetics and PHY for 10BASE-T. | Prefer DM9009 for new designs targeting 3.3V operation and LPC bus compatibility, but not for direct DP83907VF replacement. |
Compared with DP83907VF, RTL8019AS and DM9009 offer modern bus interfaces and lower power, but none integrate a standards-compliant 10BASE-T transceiver or provide native ISA/NE2000 compatibility - making DP83907VF uniquely suited for legacy retrofit and cost-sensitive ISA Ethernet adapter designs.
Availability
DP83907VF is available at Aetrix Electronics and suitable for industrial PC networking, legacy ISA-based embedded systems, PC AT-compatible network adapters, thin Ethernet node controllers, and retrocomputing platform development requiring stable component supply and long-term obsolescence mitigation.
Supply support for DP83907VF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
National Semiconductor was a U.S.-based semiconductor company specializing in analog, interface, and mixed-signal ICs before its acquisition by Texas Instruments in 2011. Its products emphasized high-reliability, industry-standard compatibility, and system-level integration.
The DP83907VF belongs to National Semiconductor's AT/LANTIC™ II family of Ethernet controllers, designed specifically to simplify implementation of IEEE 802.3-compliant 10 Mbps networks in ISA-based personal computers and industrial systems.
FAQ
What is the function of the GDLNK_led pin on the DP83907VF?
The GDLNK_led pin on the DP83907VF is an open-drain active-low output that indicates verified 10BASE-T link integrity. It asserts (goes low) only when the DP83907VF is operating in Twisted Pair Interface (TPI) mode, link integrity checking is enabled (GDLNK bit set in Configuration Register B), and the physical connection is intact. In AUI mode or when link testing is disabled, this pin remains deasserted. The DP83907VF uses this signal to drive external status LEDs without additional buffering.
Does the DP83907VF require an external crystal or oscillator?
Yes, the DP83907VF requires an external 20 MHz crystal connected between X1 (OSCIN) and X2 (OSCOUT) pins to generate the master clock for its internal timing circuits. The device does not include an on-chip oscillator; X2 must remain unconnected when using a crystal, and the crystal must meet specified load capacitance and stability requirements to ensure compliant 10 Mbps Manchester encoding/decoding performance across temperature and voltage ranges.
How does the DP83907VF handle 8-bit versus 16-bit ISA bus mode detection?
The DP83907VF detects ISA bus width at power-on reset using the MSA9 pin: a 10 kΩ pull-up to VDD enables 16-bit mode when inserted into a 16-bit slot, while an unconnected (floating) MSA9 defaults to 8-bit mode via internal pull-down. This hardware-driven detection determines data bus width, memory addressing (8 KB vs. 16 KB buffer RAM), and PROM map structure - all transparent to software once configured. The DP83907VF does not dynamically switch modes during operation.
Can the DP83907VF operate without an external EEPROM?
Yes, the DP83907VF can operate without an external EEPROM by loading Configuration Registers A/B/C directly from hardware pins (MSD0–15, MSA1–13) during reset. In this mode, the Ethernet MAC address and configuration bits are set via external pull-up/down resistors rather than EEPROM contents. However, EEPROM is required for in-situ programming, NE2000-compatible PROM space emulation, and storing user-defined data - making it essential for production-ready, field-configurable designs.
What is the purpose of the THIN output signal on the DP83907VF?
The THIN output signal on the DP83907VF is a CMOS-level logic output that goes high when the device is configured for thin coaxial (10BASE2) operation via Configuration Register B. It is intended to enable an external DC-DC converter supplying the ±12V required by 10BASE2 transceivers. This signal eliminates the need for manual jumper settings or software polling to manage power sequencing in multi-cable-type adapter designs, allowing one DP83907VF-based board to support both 10BASE2 and 10BASE-T deployments.
DP83907VF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 132-BQFP Bumpered
- Programmable:
- Not Verified
- Protocol:
- Ethernet
- Function:
- Controller
- Interface:
- ISA
- Standards:
- 10 Base-T PHY
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Supply:
- 150mA
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 132-PQFP (24.13x24.13)
- Grade:
- -
- Qualification:
- -
DP83907VF FAQ
1.How can I place an order for DP83907VF through Aetrix?
Please submit a Request for Quotation (RFQ) for DP83907VF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DP83907VF reliable?
The price and inventory of DP83907VF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DP83907VF is usually 5 days.
3.What payment methods are accepted for DP83907VF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DP83907VF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DP83907VF?
DP83907VF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DP83907VF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DP83907VF?
For technical support, including DP83907VF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DP83907VF requirements.
6.How does Aetrix verify that DP83907VF is sourced from the original manufacturer or authorized distributors?
All DP83907VF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DP83907VF meets industry standards.
7.What is the process for return or replacement of DP83907VF?
All DP83907VF units undergo pre-shipment inspection (PSI). If there is an issue with DP83907VF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DP83907VF part is unused and in its original packaging.
Return procedure for DP83907VF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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