Texas Instruments DP8390DV

Overview

DP8390DV from National Semiconductor is a microCMOS VLSI Network Interface Controller (NIC) implementing full IEEE 802.3 MAC-layer functions for Ethernet, Thin Ethernet, and StarLAN. It features dual 16-bit DMA channels, a 16-byte programmable FIFO, single 5V supply operation, and integrated bus arbitration logic - enabling direct integration into 8/16/32-bit microprocessor systems for embedded LAN node design.

For engineers reviewing the DP8390DV datasheet, DP8390DV pinout, DP8390DV application, or DP8390DV equivalent, this page delivers verified technical context, exact pin-to-function mapping, real-world buffer ring initialization requirements, CRC polynomial (AUTODIN II), and validated alternatives for legacy industrial Ethernet controller replacement.

Technical Context

The DP8390DV implements IEEE 802.3 MAC-layer packet encapsulation/decapsulation with Manchester-encoded NRZ interface to external ENDEC (e.g., DP8391), supporting preamble/SFD stripping, 32-bit FCS generation/checking using AUTODIN II polynomial, and physical/multicast/broadcast address filtering via 64-bit hash array. Its protocol PLA handles collision detection, random backoff, and loopback diagnostics across three modes.

It employs a dual-DMA architecture: Local DMA manages 256-byte receive buffer ring (configured via PSTART/PSTOP registers) with automatic linking and boundary-pointer protection; Remote DMA enables host memory transfers using PRQ/ADS1 and PWR/RACK handshaking. All timing is synchronized to external BSCK, RXC, and TXC clocks - no internal oscillator.

Key Specifications

Pinout & Package

DP8390DV is packaged in a 68-pin Plastic Leaded Chip Carrier (PLCC), per NS package code V68A. Pin functions are validated per SNLS377A datasheet Section 5.0.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Network Interface Controller applications.

Compared with DP8390DN, the DP8390DV offers identical MAC functionality in a space-efficient PLCC package suited for compact industrial PCBs, while RTL8019AS shifts focus to 10BASE-T with integrated PHY - making DP8390DV irreplaceable for coaxial and StarLAN-specific deployments where physical layer compatibility is non-negotiable.

Availability

DP8390DV is available at Aetrix Electronics and suitable for industrial control network nodes, legacy PC/AT ISA Ethernet adapters, embedded StarLAN terminals, and diagnostic test equipment requiring stable component supply across extended product lifecycles.

Supply support for DP8390DV includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

National Semiconductor was a U.S.-based semiconductor company specializing in analog, interface, and communications ICs before its acquisition by Texas Instruments in 2011. Its legacy Ethernet portfolio remains widely deployed in industrial infrastructure.

The DP8390DV belongs to National Semiconductor's early-generation IEEE 802.3 NIC family - designed specifically to enable cost-effective, standards-compliant Ethernet connectivity in resource-constrained embedded systems and PC add-in cards of the 1990s.

FAQ

What is the function of the LBK pin on the DP8390DV?

The LBK (Loopback) pin on the DP8390DV is an output that goes high when the device is configured for StarLAN ENDEC loopback mode (Transmit Configuration Register bits D2/D1 = 01 or 10). It directly controls the ENDEC's internal loopback path, enabling self-test of MAC-layer packet generation and CRC without external network traffic. This signal is not used in internal or transceiver loopback modes.

Does the DP8390DV include an integrated Ethernet PHY?

No, the DP8390DV is a pure MAC-layer controller and does not include a physical layer transceiver. It requires external components: the DP8391 Serial Network Interface (SNI) for NRZ-to-Manchester conversion and clock recovery, and the DP8392 Coaxial Transceiver Interface (CTI) for 10BASE2 or StarLAN physical signaling. The DP8390DV interfaces via RXD/TXD/NRZ signals, not MII or RMII.

How does the DP8390DV handle packet reception overflow?

When the DP8390DV's receive buffer ring fills and the DMA address reaches the Boundary Pointer, it sets the OVW bit in the Interrupt Status Register and aborts packet reception - preserving already-stored packets. Recovery requires executing a strict 11-step overflow routine including STOP command, 1.6 ms wait, loopback activation, and Boundary Pointer reset - failure to follow this sequence risks undefined NIC behavior.

What clock frequencies are required for DP8390DV operation?

The DP8390DV requires three external clocks: BSCK (bus clock, typically 5–8 MHz) for DMA timing; RXC (receive clock, derived from network signal via ENDEC, ~10 MHz for 10 Mbps) for deserializing incoming data; and TXC (transmit clock, nominally 1 MHz from ENDEC) for serializing outgoing data. No internal clock generation is provided - all timing is synchronous to these inputs.

Can the DP8390DV operate in 32-bit processor systems?

Yes, the DP8390DV supports 32-bit systems via its PRQ/ADS1 pin and LAS bit in the Data Configuration Register. When LAS = 1, PRQ becomes ADS1 and latches upper address bits A16–A31 into external latches during DMA cycles - enabling 32-bit addressing while maintaining 8/16-bit data transfers. This configuration requires external address latching logic and is documented in SNLS377A Section 5.0.