Texas Instruments DP83934CVUL-20
- Part No.:
- DP83934CVUL-20
- Manufacturer:
- Texas Instruments
- Category:
- Controllers
- Package:
- 160-BQFP
- Datasheet:
-
DP83934CVUL-20.pdf
- Description:
- IC CTRLR ORIENT NETWORK 160QFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DP83934CVUL-20 from National Semiconductor is a second-generation 10BASE-T Ethernet controller IC integrating IEEE 802.3 ENDEC, twisted-pair interface (TPI), and high-speed DMA-capable 32-bit bus interface. It operates at 20 MHz system clock, supports both big/little-endian modes, features dual 32-byte FIFOs, and delivers <5% bus bandwidth consumption in DMA transfers - deployed in embedded industrial Ethernet adapters and motherboard-integrated LAN solutions.
For engineers reviewing the DP83934CVUL-20 datasheet, DP83934CVUL-20 pinout, DP83934CVUL-20 application, or DP83934CVUL-20 equivalent, key selection criteria include integrated TPI/ENDEC compatibility with 10BASE-T physical layer, linked-list buffer management for zero-copy packet handling, selectable National/Intel vs. Motorola bus timing, and support for up to 16 address filters in legacy ISA/PCI-bridge systems.
Technical Context
The DP83934CVUL-20 implements a pipelined MAC architecture with separate receive/transmit paths, integrated Manchester encoder/decoder, and Smart Squelch-based link integrity detection. Its TPI module includes collision detection, polarity correction, jabber protection, and active link pulse generation - all operating without external transceivers when used in 10BASE-T mode.
Buffer management relies on three memory-mapped descriptor areas: Receive Resource Area (RRA), Receive Descriptor Area (RDA), and Receive Buffer Area (RBA); transmit uses Transmit Descriptor Area (TDA) and Transmit Buffer Area (TBA). The controller supports non-contiguous packet data placement and arbitrary byte-aligned buffers, enabling efficient scatter-gather DMA in 16-/32-bit systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Interface Standard | IEEE 802.3-compliant 10BASE-T Ethernet controller with integrated ENDEC and TPI - eliminates need for external transceiver in twisted-pair applications. |
| Bus Width & Mode | 32-bit non-multiplexed address/data bus with selectable National/Intel (little-endian) or Motorola (big-endian) timing - ensures drop-in compatibility with diverse 16/32-bit microprocessors. |
| FIFO Depth | Two independent 32-byte FIFOs (RX/TX) - decouples MAC timing from system bus latency, reducing packet loss under burst traffic. |
| Buffer Management | Linked-list descriptor-based scheme with RRA/RDA/RBA (RX) and TDA/TBA (TX) - enables zero-copy packet processing and dynamic resource allocation without CPU intervention. |
| Address Filtering | Hardware-accelerated filtering for up to 16 physical or multicast MAC addresses - offloads address matching from host CPU in multi-node networked devices. |
| Timer & Diagnostics | Integrated 32-bit general-purpose timer + loopback diagnostics (ENDEC, MAC, and TPI levels) - supports self-test, timing-critical protocol stacks, and field-deployable validation. |
| Power Technology | Fabricated in low-power CMOS - compatible with 5 V ±10% supply across all I/O and core domains (VCC, VCCL, RXVCC, TPVCC). |
Pinout & Package
DP83934CVUL-20 is housed in a 160-pin Plastic Quad Flat Package (PQFP) with 0.65 mm pitch, thermally optimized for industrial board-level integration. Pin functions are mode-dependent: BMODE selects between National/Intel (BMODE = 0) and Motorola (BMODE = 1) bus protocols, altering ADS/AS, MWR/MRW, INT/INT, and RDYi/DSACK signal behavior.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TXOda, TXOa, TXOb, TXOdb | TPI Transmit Outputs | Differential CMOS outputs resistively combined externally to generate 10BASE-T compliant differential transmit signal with ISI equalization. |
| RXIa, RXIb | TPI Receive Inputs | Differential inputs feeding internal amplifier and squelch logic - detect valid Manchester data and assert CRSo upon first valid edge. |
| TXLED, RXLED, COLED, POLED, LINKLED | Link Status Indicators | Active-low LED drivers synchronized to packet activity (50 ms pulse), collision, polarity reversal, and link integrity - enable real-time hardware debug without software polling. |
| BMODE | Bus Mode Select | Hardwired input determining endian format and bus control signal polarity - defines whether ADS/AS, MWR/MRW, and RDYi/DSACK pins follow Intel or Motorola timing conventions. |
| EXT, AUI/TP | Interface Configuration | EXT enables/disables internal ENDEC; AUI/TP selects between AUI (external transceiver) and TPI (integrated twisted-pair) operation - configures pin multiplexing for CRSi/COLi/RXDi/TXCi vs. CRSo/COLo/RXDo/TXCo. |
| OSCIN / OSCOUT | ENDEC Clock Source | Crystal feedback pair supporting 20 MHz fundamental-mode crystal or external oscillator - generates precise 10 MHz ENDEC clock internally via divide-by-2. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Twisted Pair Interface (TPI) | Full 10BASE-T PHY functionality including Smart Squelch, jabber protection, link pulse generation, and polarity correction - reduces BOM count by eliminating discrete transceiver ICs. |
| Auto AUI/TPI Selection | Hardware-selectable interface mode via AUI/TP pin - enables single-board design supporting both coaxial (AUI) and twisted-pair (10BASE-T) cabling without layout changes. |
| High-Speed Interruptible DMA | DMA engine consumes <5% of bus bandwidth and supports interrupt-on-completion per packet - minimizes CPU overhead in real-time embedded networking stacks. |
| Linked-List Buffer Management | Three-region RX (RRA/RDA/RBA) and two-region TX (TDA/TBA) memory layout - enables dynamic buffer allocation, scatter-gather packet assembly, and zero-copy forwarding in constrained memory systems. |
| Complete Address Filtering | On-chip CAM unit filters up to 16 unicast/multicast addresses in hardware - accelerates packet acceptance/rejection decisions before CPU involvement. |
| Full Network Management Support | Complies with IEEE 802.3 layer management standard and interfaces directly with DP83950 Repeater Interface Controller (RIC) via PCOMP pin - enables SNMP-ready repeater/bridge designs. |
Applications
| Industrial Ethernet Adapter | Legacy PC LAN Card |
|---|---|
|
Use Scenario: Retrofitting ISA-bus industrial controllers with 10BASE-T connectivity for factory-floor PLC communication. IC Role / Device Role / Timing Role: Primary MAC+PHY controller managing packet framing, Manchester encoding/decoding, and DMA-driven memory transfer over 16-bit ISA bus. Use Value: Eliminates need for external transceiver and reduces adapter component count by 3–5 parts while maintaining full IEEE 802.3 compliance at 10 Mbps. |
Use Scenario: Low-cost desktop PC LAN add-in card using shared-memory buffer architecture with legacy BIOS support. IC Role / Device Role / Timing Role: Standalone Ethernet controller interfacing to ISA bus with programmable interrupt (INT) and ready (RDYi) handshake signals. Use Value: Enables plug-and-play driver compatibility via standard register map and supports auto-negotiation-free 10BASE-T operation with minimal host-side firmware. |
| Embedded Network Bridge | Thin-Client Terminal LAN Interface |
|
Use Scenario: Dual-port bridge connecting RS-485 fieldbus to Ethernet backbone in building automation systems. IC Role / Device Role / Timing Role: One of two DP83934CVUL-20 instances handling Ethernet side with integrated TPI, paired with DP8392 for coaxial upstream. Use Value: Provides deterministic latency via hardware address filtering and loopback diagnostics - critical for time-sensitive bridging of deterministic fieldbus protocols. |
Use Scenario: Diskless thin-client terminal requiring compact, low-power wired LAN for PXE boot and remote desktop. IC Role / Device Role / Timing Role: Integrated PHY+MAC delivering 10 Mbps full-duplex link with automatic link pulse generation and polarity correction. Use Value: Achieves reliable link-up in noisy office environments via Smart Squelch and LINKLED status indication - reduces boot failure rate by >90% vs. basic PHY-only solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Ethernet controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DP83932CVUL | First-generation SONIC without integrated TPI; requires external DP8392 transceiver for 10BASE-T - lacks Smart Squelch, link pulse generation, and POLED/LINKLED indicators. | Suitable only for AUI or coaxial (10BASE2/5) deployments; cannot operate standalone in 10BASE-T without additional ICs. | Select DP83932CVUL only when reusing existing DP8392-based designs or when TPI functionality is unnecessary. |
| RTL8019AS | Nested 8/16-bit ISA interface; no integrated ENDEC/TPI - requires external 10BASE-T transformer and PHY; lacks linked-list buffer management and 32-bit DMA. | Targeted at cost-sensitive PC add-in cards with minimal firmware requirements; no native support for embedded buffer chaining or network management buses. | Choose RTL8019AS for ultra-low-cost legacy PC applications where BOM reduction is secondary to gate count and licensing simplicity. |
Compared with DP83934CVUL-20, DP83932CVUL requires external transceiver support and offers no TPI diagnostics, while RTL8019AS lacks integrated PHY and advanced buffer management - making DP83934CVUL-20 uniquely suited for compact, self-contained 10BASE-T embedded designs demanding hardware-accelerated packet handling and link integrity assurance.
Availability
DP83934CVUL-20 is available at Aetrix Electronics and suitable for industrial Ethernet adapters, legacy PC LAN cards, embedded network bridges, and thin-client terminal LAN interfaces requiring stable component supply and long-term obsolescence mitigation.
Supply support for DP83934CVUL-20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
National Semiconductor was a U.S.-based semiconductor company specializing in analog, interface, and communications ICs before its acquisition by Texas Instruments in 2011. Known for high-reliability industrial-grade components and comprehensive technical documentation.
The SONIC-T product line was designed specifically for embedded Ethernet connectivity in resource-constrained 16-/32-bit systems - emphasizing low CPU overhead, hardware-accelerated packet filtering, and seamless integration with ISA, VME, and custom bus architectures.
FAQ
What is the maximum data rate supported by the DP83934CVUL-20?
The DP83934CVUL-20 is a 10 Mbps IEEE 802.3-compliant Ethernet controller. It supports full-duplex 10BASE-T operation using its integrated twisted-pair interface and ENDEC. The 20 MHz clock input drives internal timing circuits that derive precise 10 MHz transmit/receive clocks - no oversampling or rate adaptation is performed. DP83934CVUL-20 does not support 100BASE-TX or higher speeds.
Does the DP83934CVUL-20 require an external crystal or oscillator?
Yes, the DP83934CVUL-20 requires a 20 MHz clock source connected between OSCIN and OSCOUT pins. This may be either a parallel-resonant fundamental-mode crystal or a buffered 20 MHz CMOS oscillator module. The internal ENDEC divides this by two to generate its 10 MHz reference - no internal PLL or frequency synthesis is provided, so clock accuracy directly impacts Manchester timing compliance.
Can the DP83934CVUL-20 operate in both National/Intel and Motorola bus modes simultaneously?
No, the DP83934CVUL-20 operates in only one bus mode at a time, selected by the BMODE pin level during power-up. BMODE = 0 configures National/Intel timing (ADS strobe, MWR polarity, RDYi handshake), while BMODE = 1 enables Motorola timing (AS strobe, MRW polarity, DSACK0/1 handshake). Mixed-mode operation is not supported - the pin must be hardwired to VCC or GND before initialization.
How does the DP83934CVUL-20 handle packet reception without CPU intervention?
The DP83934CVUL-20 uses a three-area linked-list buffer model: RRA allocates descriptors, RDA stores status/control flags, and RBA holds packet data. Upon frame arrival, the TPI and ENDEC pass decoded bits directly into RBA, then update RDA with length/error flags - triggering DMA completion interrupt without CPU copying. This zero-copy mechanism is enabled by configuring DCR and CSR registers prior to activation.
Is the DP83934CVUL-20 still in production or considered obsolete?
The DP83934CVUL-20 is marked "Obsolete" in its official datasheet (SNLS088A, July 1995) and has been discontinued by Texas Instruments (successor to National Semiconductor). However, Aetrix Electronics maintains verified legacy inventory with full traceability, conforming to original specifications and packaging - supporting repair, replacement, and long-life industrial program continuity.
DP83934CVUL-20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 160-BQFP
- Programmable:
- Not Verified
- Protocol:
- Ethernet
- Function:
- Controller
- Interface:
- Parallel
- Standards:
- 10 Base-T PHY
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Supply:
- 140mA
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 160-PQFP (28x28)
- Grade:
- -
- Qualification:
- -
DP83934CVUL-20 FAQ
1.How can I place an order for DP83934CVUL-20 through Aetrix?
Please submit a Request for Quotation (RFQ) for DP83934CVUL-20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DP83934CVUL-20 reliable?
The price and inventory of DP83934CVUL-20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DP83934CVUL-20 is usually 5 days.
3.What payment methods are accepted for DP83934CVUL-20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DP83934CVUL-20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DP83934CVUL-20?
DP83934CVUL-20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DP83934CVUL-20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DP83934CVUL-20?
For technical support, including DP83934CVUL-20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DP83934CVUL-20 requirements.
6.How does Aetrix verify that DP83934CVUL-20 is sourced from the original manufacturer or authorized distributors?
All DP83934CVUL-20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DP83934CVUL-20 meets industry standards.
7.What is the process for return or replacement of DP83934CVUL-20?
All DP83934CVUL-20 units undergo pre-shipment inspection (PSI). If there is an issue with DP83934CVUL-20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DP83934CVUL-20 part is unused and in its original packaging.
Return procedure for DP83934CVUL-20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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