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Texas Instruments DP83936AVUL-20
- Part No.:
- DP83936AVUL-20
- Manufacturer:
- Texas Instruments
- Category:
- Controllers
- Package:
- 160-BQFP
- Datasheet:
-
DP83936AVUL-20.pdf
- Description:
- IC CTRLR ORIENT NETWORK 160QFP
- Quantity:
- Payment:
- Shipping:
Inventory:2,578
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Product details
Overview
DP83936AVUL-20 from National Semiconductor is a second-generation 10BASE-T Ethernet controller IC with integrated IEEE 802.3 ENDEC and twisted-pair interface, supporting full-duplex operation at 20 MHz system clock, 32-bit non-multiplexed bus interface, and linked-list DMA buffer management for zero-copy packet handling in embedded network adapters and motherboard LAN controllers.
For engineers reviewing the DP83936AVUL-20 datasheet, DP83936AVUL-20 pinout, DP83936AVUL-20 application, or DP83936AVUL-20 equivalent, key selection criteria include its integrated TPI/ENDEC, dual 32-byte FIFOs, support for big/little-endian microprocessors, and compatibility with legacy 16-/32-bit ISA and VME bus architectures requiring deterministic interrupt latency and minimal CPU bus bandwidth consumption.
Technical Context
The DP83936AVUL-20 implements a pipelined MAC layer with independent transmit/receive paths, integrated Manchester encoder/decoder, and differential twisted-pair transceiver logic - all operating from a single 20 MHz crystal input (OSCIN/OSCOUT). Its ENDEC unit handles preamble detection, SFD recognition, CRC-32 generation/checking, and collision sensing without external components when configured for internal TPI mode (EXT = 0, AUI/TP = 0).
Buffer management uses three memory regions: Receive Resource Area (RRA), Receive Buffer Area (RBA), and Receive Descriptor Area (RDA); plus Transmit Descriptor Area (TDA) and Transmit Buffer Area (TBA). The controller supports scatter-gather packet transmission and reception with descriptors aligned on 16-byte boundaries, enabling efficient use of fragmented system memory.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Interface Standard | IEEE 802.3 10BASE-T compliant with integrated ENDEC and TPI - enables single-chip 10 Mbps Ethernet connectivity without external transceiver or line driver. |
| System Clock | 20 MHz - defines maximum bus transfer rate and internal timing for ENDEC, MAC, and FIFO operations; matches DP83936AVUL-20 variant designation. |
| Bus Width | 32-bit non-multiplexed address/data - reduces bus cycle overhead and supports high-throughput DMA transfers with <5% CPU bus bandwidth utilization. |
| FIFO Depth | Two independent 32-byte FIFOs - decouples MAC layer timing from system bus latency, absorbing bursty traffic and smoothing data flow to/from memory. |
| Address Filtering | Hardware CAM supporting up to 16 physical/multicast addresses - offloads address matching from host CPU, enabling selective packet acceptance in promiscuous or multicast-aware applications. |
| Timer | 32-bit general-purpose timer - provides programmable timebase for protocol timeouts, statistics sampling, or system watchdog functions without external components. |
| Power Technology | Low-power CMOS process - enables operation at 5 V with reduced thermal dissipation suitable for dense PCB layouts in industrial and telecom equipment. |
Pinout & Package
DP83936AVUL-20 is housed in a 160-pin Plastic Quad Flat Package (PQFP) with 0.65 mm lead pitch, designed for surface-mount assembly and thermal management in space-constrained network interface cards and embedded controllers.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TXOda, TXOa, TXOb, TXOdb | Twisted Pair Transmit Outputs | Differential CMOS-level outputs resistively combined externally to generate 10BASE-T compliant differential signal with ISI compensation. |
| RXIa, RXIb | Twisted Pair Receive Inputs | Differential inputs feeding internal amplifier and ENDEC - detect valid Manchester-encoded data and carrier presence on unshielded twisted pair. |
| EXT | External ENDEC Select | Logic-level control (VCC/GND) enabling/disabling internal ENDEC; determines pin function mapping for CRS/CD/RX/TX signals. |
| AUI/TP | Interface Mode Select | Selects between AUI (external transceiver) and TPI (integrated twisted-pair) operation; configures internal signal routing and driver types. |
| BMODE | Bus Mode Configuration | Defines endianess (Intel/National = little-endian, Motorola = big-endian) and controls AS/ADS, MRW/MWR, INT/INT pin behavior per bus architecture. |
| D31–D0 | Bi-directional Data Bus | 32-bit wide data path supporting both slave register access (D15–D0) and master DMA transfers (D31–D0 or D15–D0 depending on configuration). |
| RA5–RA0 | Register Address Bus | 6-bit address lines selecting one of 64 internal registers including command, status, control, CAM, and timer registers. |
| OSCIN / OSCOUT | Crystal Oscillator Interface | Connects to 20 MHz fundamental-mode crystal or external oscillator to drive ENDEC, MAC, and timing logic with precise 10 MHz derived clocks. |
Key Features
| Feature | Design Value |
|---|---|
| Full-duplex operation | Enables simultaneous transmit/receive at 10 Mbps without CSMA/CD arbitration - eliminates collisions and doubles effective throughput in point-to-point links. |
| Linked-list buffer management | Eliminates packet copying by allowing receive/transmit descriptors to reference non-contiguous memory blocks - reduces CPU overhead and memory fragmentation in real-time systems. |
| Auto AUI/TPI selection | Hardware pin (AUI/TP) configures interface mode at power-up - simplifies board design for multi-standard compatibility without firmware reconfiguration. |
| Integrated loopback diagnostics | On-chip ENDEC loopback (LBK pin) enables functional verification of MAC, ENDEC, and TPI without external cabling or test equipment. |
| Network management support | Complies with IEEE 802.3 layer management standard - provides tally counters, CAM registers, and status reporting required for SNMP-based monitoring in repeaters and bridges. |
| Programmable user outputs | Four EXUSRx pins (EXUSR0–EXUSR3) configurable as GPIO after bus master acquisition - enables hardware signaling for link status, activity, or custom control logic. |
Applications
| Industrial Ethernet Adapter | Legacy PC Network Card |
|---|---|
Use Scenario: Adding 10BASE-T connectivity to PLCs and motion controllers using ISA or VME backplanes with limited CPU resources. IC Role / Device Role / Timing Role: Primary MAC+PHY controller handling frame assembly, CRC calculation, Manchester encoding/decoding, and twisted-pair signal conditioning. Use Value: Integrated ENDEC and TPI eliminate discrete transceiver components, reducing BOM cost and PCB area while maintaining compatibility with existing 10 Mbps infrastructure. |
Use Scenario: Retrofitting older desktop PCs with NE2000-compatible Ethernet capability via 16-bit ISA slot. IC Role / Device Role / Timing Role: Drop-in replacement for DP83932/DP83935 controllers with enhanced full-duplex and descriptor-based DMA support. Use Value: Backward-compatible register map and interrupt behavior enable reuse of existing DOS/Windows drivers while delivering improved throughput via zero-copy buffer management. |
| Embedded Bridge Controller | Telecom Terminal Equipment |
Use Scenario: Implementing store-and-forward bridging between two 10BASE-T segments in managed hub or repeater chassis. IC Role / Device Role / Timing Role: Dual-port Ethernet controller managing ingress/egress frame forwarding, address learning, and collision domain isolation. Use Value: Hardware CAM filtering and tally counters reduce software processing load, enabling deterministic latency and scalable port density in multi-port bridge designs. |
Use Scenario: Integrating LAN interface into PBX maintenance terminals, DSLAM management modules, or remote telemetry units. IC Role / Device Role / Timing Role: Reliable, low-power Ethernet endpoint providing out-of-band management access over twisted-pair cabling. Use Value: Low-power CMOS process and robust squelch/collision detection ensure stable operation in electrically noisy telecom environments with long cable runs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Ethernet controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DP83935AVUL-20 | Lacks integrated twisted-pair interface; requires external DP8392 coaxial transceiver or separate TPI IC. | Suitable only for 10BASE2/10BASE5 or hybrid AUI+TPI designs - not a drop-in replacement for DP83936AVUL-20's single-chip 10BASE-T solution. | Select DP83935AVUL-20 only if legacy coaxial infrastructure or modular transceiver flexibility is required. |
| RTL8019AS | NE2000-compatible ISA controller with integrated 10BASE-T PHY but no full-duplex support or linked-list DMA. | Targets cost-sensitive PC add-in cards; lacks SONIC-T's advanced buffer management and network management features. | Choose RTL8019AS for simple plug-and-play DOS/Windows compatibility where full-duplex or deterministic latency is not required. |
Compared with DP83936AVUL-20, DP83935AVUL-20 requires additional transceiver components and offers no native TPI, while RTL8019AS provides simpler integration but sacrifices full-duplex operation, advanced descriptor-based buffering, and IEEE 802.3 layer management compliance - making DP83936AVUL-20 optimal for performance-critical embedded bridge and industrial adapter designs.
Availability
DP83936AVUL-20 is available at Aetrix Electronics and suitable for industrial Ethernet adapters, legacy PC network cards, and embedded bridge controllers requiring stable component supply and long-term obsolescence management.
Supply support for DP83936AVUL-20 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
National Semiconductor was a U.S.-based semiconductor company specializing in analog, interface, and communications ICs before its acquisition by Texas Instruments in 2011; known for high-reliability industrial and telecom solutions.
The DP83936AVUL-20 belongs to the SONIC-T family of Systems-Oriented Network Interface Controllers, designed specifically for embedded 32-/16-bit systems needing integrated 10BASE-T Ethernet with minimal CPU overhead and deterministic real-time behavior.
FAQ
What is the primary function of the DP83936AVUL-20 in an Ethernet system?
The DP83936AVUL-20 serves as a complete 10BASE-T Ethernet controller with integrated MAC, ENDEC, and twisted-pair interface - handling frame assembly/disassembly, CRC generation/checking, Manchester encoding/decoding, and differential signal driving/receiving. It operates as a bus-master DMA device, minimizing host CPU involvement during packet transfers while maintaining strict IEEE 802.3 compliance. Its role is foundational in legacy embedded LAN interfaces where software stack efficiency and hardware determinism are critical.
Does the DP83936AVUL-20 support full-duplex operation, and how is it enabled?
Yes, the DP83936AVUL-20 supports full-duplex operation as a configurable feature. It is enabled via the Full Duplex Control bit in the Transmit Control Register (TCR), and requires proper initialization of the ENDEC and TPI modules. When activated, the DP83936AVUL-20 bypasses CSMA/CD arbitration and allows simultaneous transmission and reception at 10 Mbps - verified through loopback testing and documented in Section 3.3.3 and Register 6.4.4 of the SNLS105A datasheet.
What package type and pin count does the DP83936AVUL-20 use?
The DP83936AVUL-20 uses a 160-pin Plastic Quad Flat Package (PQFP) with 0.65 mm lead pitch, as confirmed in the "Features" section and Pin Description table of the SNLS105A datasheet. This package supports fine-pitch surface-mount assembly and provides dedicated power/ground pins for digital, ENDEC, and TPI sections - essential for noise isolation in mixed-signal Ethernet applications.
Can the DP83936AVUL-20 operate with external ENDECs, and how is that configured?
Yes, the DP83936AVUL-20 can interface with external ENDECs such as the DP8392 series. Configuration is performed using the EXT pin: tying EXT to ground (0 V) enables the internal ENDEC and activates TPI pins (TXOda, RXIa, etc.), while tying EXT to VCC selects external ENDEC mode and repurposes pins like CRSo/CRSi and COLo/COLi as I/O interfaces. This dual-mode capability is explicitly defined in Table 2-1 and Section 3.2.2 of the SNLS105A datasheet.
What are the key timing requirements for the DP83936AVUL-20's oscillator input?
The DP83936AVUL-20 requires a 20 MHz fundamental-mode crystal or oscillator connected between OSCIN and OSCOUT pins, as specified in Section 8.1.3 and AC Timing Test Conditions (Section 10.0) of SNLS105A. This input drives internal PLL circuitry to generate precise 10 MHz transmit/receive clocks and synchronize ENDEC, MAC, and FIFO operations - deviation beyond ±100 ppm may cause frame synchronization failure or CRC errors in sustained traffic.
DP83936AVUL-20 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 160-BQFP
- Programmable:
- Not Verified
- Protocol:
- Ethernet
- Function:
- Controller
- Interface:
- Parallel
- Standards:
- 10 Base-T PHY
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Supply:
- 140mA
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 160-PQFP (28x28)
- Grade:
- -
- Qualification:
- -
DP83936AVUL-20 FAQ
1.How can I place an order for DP83936AVUL-20 through Aetrix?
Please submit a Request for Quotation (RFQ) for DP83936AVUL-20 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DP83936AVUL-20 reliable?
The price and inventory of DP83936AVUL-20 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DP83936AVUL-20 is usually 5 days.
3.What payment methods are accepted for DP83936AVUL-20?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DP83936AVUL-20 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DP83936AVUL-20?
DP83936AVUL-20 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DP83936AVUL-20 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DP83936AVUL-20?
For technical support, including DP83936AVUL-20 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DP83936AVUL-20 requirements.
6.How does Aetrix verify that DP83936AVUL-20 is sourced from the original manufacturer or authorized distributors?
All DP83936AVUL-20 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DP83936AVUL-20 meets industry standards.
7.What is the process for return or replacement of DP83936AVUL-20?
All DP83936AVUL-20 units undergo pre-shipment inspection (PSI). If there is an issue with DP83936AVUL-20, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DP83936AVUL-20 part is unused and in its original packaging.
Return procedure for DP83936AVUL-20:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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