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Texas Instruments DP83936AVUL-25
- Part No.:
- DP83936AVUL-25
- Manufacturer:
- Texas Instruments
- Category:
- Controllers
- Package:
- 160-BQFP
- Datasheet:
-
DP83936AVUL-25.pdf
- Description:
- IC CTRLR ORIENT NETWORK 160QFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,838
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Product details
Overview
DP83936AVUL-25 from National Semiconductor is a second-generation 10BASE-T Ethernet controller IC implementing full-duplex IEEE 802.3 MAC, integrated ENDEC, and twisted-pair interface in a single 160-pin PQFP package. It delivers <5% bus bandwidth DMA utilization, supports both big/little-endian microprocessors, and enables direct system memory packet buffering without intermediate copy. Used in embedded 32-bit motherboard and PC adapter designs requiring low-overhead 10 Mbps wired connectivity.
For engineers reviewing the DP83936AVUL-25 datasheet, DP83936AVUL-25 pinout, DP83936AVUL-25 application, or DP83936AVUL-25 equivalent, key selection criteria include its selectable National/Intel vs. Motorola bus mode, auto AUI/TPI media selection, integrated 32-byte TX/RX FIFOs, linked-list buffer management architecture, and support for up to 16 physical/multicast address filtering.
Technical Context
The DP83936AVUL-25 integrates three core functional blocks: a Twisted Pair Interface (TPI) with Smart Squelch and polarity detection, an IEEE 802.3-compliant ENDEC with Manchester encoding/decoding, and a Media Access Control (MAC) unit supporting full-duplex operation and collision detection. Its DMA engine operates at up to 25 MHz system clock frequency and uses asynchronous bus arbitration with programmable wait-state control via RDYi/RDYo or DSACK0/DSACK1.
Buffer management relies on three distinct memory regions: Receive Resource Area (RRA), Receive Buffer Area (RBA), and Receive Descriptor Area (RDA); plus Transmit Descriptor Area (TDA) and Transmit Buffer Area (TBA). The 32-bit general-purpose timer, loopback diagnostics, and CAM-based address filtering (16 entries) are implemented in dedicated on-chip logic with no external dependencies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Interface Standard | IEEE 802.3-compliant 10BASE-T full-duplex Ethernet controller with integrated ENDEC and TPI |
| Bus Width & Mode | 32-bit non-multiplexed address/data bus; configurable National/Intel (little-endian) or Motorola (big-endian) mode |
| FIFO Depth | Two independent 32-byte FIFOs - one for transmit, one for receive - reducing host CPU interrupt frequency |
| Address Filtering | On-chip CAM supports filtering of up to 16 physical or multicast MAC addresses without host software intervention |
| Timer | Integrated 32-bit general-purpose timer usable for packet timing, watchdog, or system scheduling functions |
| Power Supply | Single +5 V supply for digital core (VCC1–VCC9), separate +5 V rails for ENDEC (VCCL, TXVCC, RXVCC) and TPI (TPVCC, RXTVCC) |
| Operating Frequency | 25 MHz system clock input (OSCIN/OSCOUT); generates internal 10 MHz TX/RX clocks for 10BASE-T compliance |
Pinout & Package
DP83936AVUL-25 is housed in a 160-pin Plastic Quad Flat Package (PQFP) with 0.65 mm lead pitch, designed for surface-mount assembly on industrial and embedded PCBs. Pin functions are dual-mode configurable via BMODE and support both National/Intel and Motorola bus protocols.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D31–D0 | Data Bus | Bidirectional 32-bit data path; driven by SONIC-T during master cycles, tri-stated when slave; D15–D0 used for 16-bit transfers |
| A31–A1 | Address Bus | 31-line output for DMA addressing; aligned to word boundaries, enabling efficient burst transfers to system memory |
| RA5–RA0 | Register Address Bus | 6-bit input selecting internal register map (CSR, DCR, RCR, TCR, ISR, etc.) during CPU register access |
| TXOda, TXOa, TXOb, TXOdb | TPI Transmit Outputs | Differential CMOS-level outputs resistively combined externally to generate 10BASE-T compliant differential transmit signal with ISI equalization |
| RXIa, RXIb | TPI Receive Inputs | Differential inputs feeding internal amplifier and squelch circuit; detect valid 10BASE-T link pulses and packet polarity reversals |
| TXLED, RXLED, COLED, POLED, LINKLED | Link Status Indicators | Active-low open-collector outputs providing real-time hardware visibility into transmit, receive, collision, polarity error, and link integrity states |
| EXT, AUI/TP, LNKDIS, LOWSQL | Configuration Inputs | Hardware-selectable modes: internal/external ENDEC, AUI/TPI media interface, link test enable/disable, and low-squelch threshold |
Key Features
| Feature | Design Value |
|---|---|
| Full-Duplex Operation | Enables simultaneous transmit/receive at 10 Mbps without CSMA/CD contention, supported by dedicated MAC logic and dual FIFOs |
| Linked-List Buffer Management | Eliminates packet copying by allowing scatter-gather DMA across non-contiguous memory regions using descriptor chains in RRA/RDA/TDA |
| Auto AUI/TPI Selection | Hardware pin (AUI/TP) selects between external coaxial transceiver interface or integrated twisted-pair PHY - no firmware reconfiguration needed |
| Integrated ENDEC + TPI | Single-chip 10BASE-T solution requiring only magnetics and RJ-45 connector; no external encoder/decoder or line driver ICs required |
| Network Management Support | Complies with IEEE 802.3 layer management standard; provides tally counters, CAM registers, and status flags for SNMP-compatible monitoring |
| Loopback Diagnostics | Internal ENDEC loopback mode (via LBK pin) enables hardware-level validation of MAC-to-PHY data path without external cabling or network traffic |
Applications
| Industrial Ethernet Node | Legacy PC Network Adapter |
|---|---|
|
Use Scenario: Real-time PLC communication over unshielded twisted-pair cabling in factory automation cabinets with EMI exposure. IC Role / Device Role / Timing Role: Primary MAC+PHY controller handling frame assembly/disassembly, CRC generation/checking, and Manchester encoding/decoding at 10 Mbps. Use Value: Integrated TPI and ENDEC eliminate external components; full-duplex mode avoids bus arbitration delays critical for deterministic I/O response. |
Use Scenario: ISA-bus Ethernet card for DOS/Windows 3.1-era industrial PCs requiring plug-and-play compatibility with legacy drivers. IC Role / Device Role / Timing Role: System-oriented network interface controller interfacing directly to 16-bit ISA bus with National/Intel mode timing and IRQ-driven interrupt signaling. Use Value: Configurable bus mode and built-in address filtering simplify driver development; 32-byte FIFOs reduce CPU overhead per packet versus older 8-bit NICs. |
| Embedded Bridge Module | Repeater Controller |
|
Use Scenario: Two-port transparent bridge connecting 10BASE-T segments in building-wide security camera networks. IC Role / Device Role / Timing Role: Dual-port bridging controller performing store-and-forward forwarding, source/destination address learning, and port isolation using CAM and tally counters. Use Value: On-chip CAM supports 16 learned addresses; full-duplex operation allows concurrent ingress/egress on each port without throughput penalty. |
Use Scenario: Four-port repeater hub managing collision domains in legacy office LANs with mixed 10BASE-T and 10BASE2 segments. IC Role / Device Role / Timing Role: Repeater interface controller synchronizing signal regeneration across ports using ENDEC loopback and collision translation logic. Use Value: Integrated collision translator and CRS/COL signals enable precise inter-port collision detection; PCOMP pin interfaces directly with DP83950 RIC for management packet compression. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Ethernet controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DP83932AVUL | First-generation SONIC without integrated TPI; requires external DP8392 coaxial transceiver or discrete ENDEC+line driver | Suitable only for AUI or 10BASE2/5 systems; lacks 10BASE-T PHY, full-duplex MAC, and Smart Squelch | Select DP83932AVUL only when upgrading legacy coaxial infrastructure where TPI integration is unnecessary |
| RTL8019AS | ISA-bus NE2000-compatible controller with integrated 10BASE-T PHY but no full-duplex MAC or CAM-based address filtering | Designed for PC BIOS compatibility and DOS driver reuse; lacks linked-list DMA and network management registers | Choose RTL8019AS for cost-sensitive PC add-in cards needing NE2000 software compatibility, not for embedded real-time systems |
Compared with DP83936AVUL-25, DP83932AVUL requires two chips for 10BASE-T operation and offers no full-duplex capability, while RTL8019AS sacrifices advanced buffer management and IEEE 802.3 layer management for broad software compatibility - making DP83936AVUL-25 optimal for performance-critical embedded Ethernet nodes requiring hardware-accelerated packet handling.
Availability
DP83936AVUL-25 is available at Aetrix Electronics and suitable for industrial Ethernet node, legacy PC network adapter, embedded bridge module, and repeater controller applications requiring stable component supply and long-term obsolescence management.
Supply support for DP83936AVUL-25 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
National Semiconductor was a U.S.-based semiconductor company specializing in analog, interface, and communications ICs before its acquisition by Texas Instruments in 2011.
The DP83936AVUL-25 belongs to the SONIC-T family of Systems-Oriented Network Interface Controllers, designed specifically for high-integration, low-CPU-overhead 10 Mbps Ethernet implementations in embedded and PC-architecture systems.
FAQ
What is the primary function of the DP83936AVUL-25 in an Ethernet system?
The DP83936AVUL-25 serves as a complete 10BASE-T Ethernet controller IC, integrating MAC, ENDEC, and twisted-pair interface functions. It handles frame transmission and reception, CRC calculation, Manchester encoding/decoding, and differential signal driving/receiving - all within a single chip. Its design eliminates the need for external PHY or transceiver components in 10BASE-T applications, making DP83936AVUL-25 ideal for compact, low-component-count Ethernet nodes.
Does the DP83936AVUL-25 support full-duplex operation, and how is it enabled?
Yes, the DP83936AVUL-25 supports full-duplex operation through dedicated MAC logic and dual 32-byte FIFOs. Full-duplex mode is enabled via software configuration of the Transmit Control Register (TCR) and Receive Control Register (RCR), along with proper initialization of the CAM and descriptor areas. Hardware pin AUI/TP must be set to TPI mode (low), and EXT must be high to activate the internal ENDEC and TPI - ensuring DP83936AVUL-25 operates without CSMA/CD contention.
How does the DP83936AVUL-25 manage memory buffers without intermediate packet copying?
The DP83936AVUL-25 uses a linked-list descriptor architecture with three receive memory regions (RRA, RBA, RDA) and two transmit regions (TDA, TBA). The host CPU populates descriptors in RRA/TDA pointing to packet buffers in RBA/TBA. The SONIC-T DMA engine reads descriptors and moves data directly between those buffers and the MAC, eliminating CPU-mediated copy operations. This architecture is central to DP83936AVUL-25's sub-5% bus bandwidth utilization claim.
What are the key differences between National/Intel and Motorola bus modes on the DP83936AVUL-25?
The BMODE pin selects between National/Intel (BMODE = 0, little-endian) and Motorola (BMODE = 1, big-endian) bus protocols. This affects byte ordering, strobe polarity (ADS vs. AS), read/write signaling (MWR vs. MRW), and handshake signals (RDYi vs. DSACK0/DSACK1). Both modes support 16- or 32-bit data transfers, but timing diagrams and control signal definitions differ - requiring matching firmware and PCB layout. DP83936AVUL-25's flexibility allows seamless integration with diverse microprocessor families.
Can the DP83936AVUL-25 operate with an external ENDEC, and what pins control this?
Yes, the DP83936AVUL-25 can interface with an external ENDEC by asserting EXT = 1 (high), which disables the internal ENDEC and reconfigures pins CRSo/CRSi, COLo/COLi, RXDo/RXDi, RXCo/RXCi, and TXCo/TXCi for external signal routing. In this mode, the SONIC-T relies on the external device for Manchester encoding/decoding and collision detection. This capability makes DP83936AVUL-25 adaptable to non-10BASE-T media like 10BASE2 or custom PHY implementations.
DP83936AVUL-25 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 160-BQFP
- Programmable:
- Not Verified
- Protocol:
- Ethernet
- Function:
- Controller
- Interface:
- Parallel
- Standards:
- 10 Base-T PHY
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Supply:
- 140mA
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 160-PQFP (28x28)
- Grade:
- -
- Qualification:
- -
DP83936AVUL-25 FAQ
1.How can I place an order for DP83936AVUL-25 through Aetrix?
Please submit a Request for Quotation (RFQ) for DP83936AVUL-25 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DP83936AVUL-25 reliable?
The price and inventory of DP83936AVUL-25 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DP83936AVUL-25 is usually 5 days.
3.What payment methods are accepted for DP83936AVUL-25?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DP83936AVUL-25 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DP83936AVUL-25?
DP83936AVUL-25 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DP83936AVUL-25 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DP83936AVUL-25?
For technical support, including DP83936AVUL-25 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DP83936AVUL-25 requirements.
6.How does Aetrix verify that DP83936AVUL-25 is sourced from the original manufacturer or authorized distributors?
All DP83936AVUL-25 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DP83936AVUL-25 meets industry standards.
7.What is the process for return or replacement of DP83936AVUL-25?
All DP83936AVUL-25 units undergo pre-shipment inspection (PSI). If there is an issue with DP83936AVUL-25, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DP83936AVUL-25 part is unused and in its original packaging.
Return procedure for DP83936AVUL-25:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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