My Inquiry
My Account
Texas Instruments DRA726BPL1ABCRQ1
- Part No.:
- DRA726BPL1ABCRQ1
- Manufacturer:
- Texas Instruments
- Category:
- Microprocessors
- Package:
- 760-BFBGA, FCBGA
- Datasheet:
-
DRA726BPL1ABCRQ1.pdf
- Description:
- IC MPU DRA72X CORTEX-A15 760BGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,778
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DRA726BPL1ABCRQ1 from Texas Instruments is an AEC-Q100 qualified automotive infotainment applications processor featuring a single Arm® Cortex®-A15 CPU core, one C66x VLIW DSP core, 512KB on-chip L3 RAM with ECC, dual Cortex-M4 IPUs, and a PowerVR™ SGX544 3D GPU - deployed in digital radio decoding, rear-seat entertainment, and ADAS-integrated HMI systems.
For engineers reviewing the DRA726BPL1ABCRQ1 datasheet, DRA726BPL1ABCRQ1 pinout, DRA726BPL1ABCRQ1 application, or DRA726BPL1ABCRQ1 equivalent, key selection considerations include DDR3-1333 support (667 MHz), HDMI 1.4a compliance, PCIe Gen2 dual-lane capability, dual DCAN 2.0B interfaces, and 215 GPIOs with configurable I/O voltage domains for automotive-grade signal integrity and thermal reliability.
Technical Context
The DRA726BPL1ABCRQ1 implements a heterogeneous multi-core architecture with tightly coupled interconnects: Level 3 (L3) and Level 4 (L4) interconnects route traffic between the Cortex-A15, C66x DSP, IPU subsystems, and peripherals including EMIF, GPMC, and PCIe. Its IVA-HD subsystem handles full-HD video (1920×1080p at 60 fps) with hardware-accelerated encoding/decoding via VPE and BB2D (Vivante GC320).
Power management integrates dynamic voltage and frequency scaling across multiple independent power domains, while security features include hardware crypto accelerators, JTAG lock, secure ROM/boot, and customer-programmable keys (Silicon Revision 2.1). The device supports boot from QSPI, eMMC, SDIO, SATA, or PCIe, with configurable reset sequencing per AEC-Q100 requirements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Single Arm® Cortex®-A15 @ up to 1.5 GHz - delivers high-throughput control and OS execution for Linux-based infotainment stacks. |
| DSP Core | One TI C66x VLIW floating-point DSP - provides object-code compatibility with C64x+/C67x and 32×16-bit fixed-point multiply capability per cycle for audio/radio algorithms. |
| On-Chip RAM | 512KB OCMC RAM with SECDED ECC - enables deterministic low-latency access for real-time firmware and safety-critical code segments. |
| External Memory | DDR3/DDR3L EMIF supporting up to 2GB at 1333 MT/s - meets bandwidth demands of concurrent video decode, graphics rendering, and navigation data processing. |
| Video Output | HDMI 1.4a + DVI 1.0 compliant encoder with three independent pipelines - supports simultaneous display of instrument cluster, media UI, and rear-seat video. |
| Connectivity | Dual DCAN 2.0B, 2-port Gigabit Ethernet switch (MII/RMII/RGMII), PCIe Gen2 (2×5 Gbps lanes), USB 3.0 DRD + dual USB 2.0 OTG - enables CAN bus integration, OTA updates, and high-speed peripheral expansion. |
| Security | Hardware AES/SHA/DES accelerators, secure boot ROM, JTAG lock, firewalls, and silicon-revision 2.1 customer-programmable keys - satisfies automotive functional safety and secure boot requirements. |
| Package | 760-pin FCBGA (ABC), 23 mm × 23 mm, 0.8-mm pitch - designed for automotive PCB thermal dissipation and mechanical robustness under extended temperature operation. |
Pinout & Package
Package: 760-ball FCBGA (ABC), 23.0 mm × 23.0 mm, 0.8-mm pitch, RoHS-compliant, qualified per AEC-Q100 Grade 2 (–40°C to +105°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ddr1_ck / ddr1_nck | DDR3 Clock Pair | Differential clock inputs for DDR3 interface - require matched trace length and controlled impedance (100 Ω differential) to meet setup/hold timing at 667 MHz. |
| porz / rstoutn | Power-On Reset Control | Active-low POR input and open-drain reset output - used for system-level reset coordination and watchdog recovery in automotive ECU designs. |
| dcana_tx / dcana_rx | DCAN1 Differential Pair | High-speed CAN 2.0B physical layer interface - supports 1 Mbps operation with integrated termination and fault protection for vehicle network communication. |
| hdmi_tx_clk / hdmi_tx_data[2:0] | HDMI TMDS Channel | Transition-minimized differential signaling outputs - drive HDMI 1.4a-compliant displays with HDCP-ready content protection paths. |
| gmac_sw0_mii_txen / gmac_sw0_mii_rxd[3:0] | Gigabit Ethernet MII Interface | 24-pin MII/RMII/RGMII-configurable port - enables time-sensitive networking (TSN) readiness and AVB-capable audio/video streaming over automotive Ethernet. |
Key Features
| Feature | Design Value |
|---|---|
| IVA-HD Subsystem | Hardware-accelerated 1080p60 video encode/decode with H.264/VC1/MPEG-4 support - reduces CPU load and enables concurrent multimedia playback and navigation rendering. |
| VPE + BB2D | Video Processing Engine + Vivante GC320 2D accelerator - enables real-time video scaling, blending, and UI compositing without frame drops in multi-display configurations. |
| Dual Cortex-M4 IPUs | Independent image processing units offloading vision preprocessing (e.g., camera calibration, lens distortion correction) from main A15/DSP cores - improves latency and determinism for ADAS sensor fusion. |
| PCIe Gen2 Dual-Lane | Configurable as one 2-lane or two 1-lane ports - supports high-bandwidth expansion for cellular modems, radar processors, or external storage without requiring additional bridge ICs. |
| Secure Boot & TEE | ROM-based secure boot with SHA-256 verification and runtime Trusted Execution Environment (on HS variants) - enforces chain-of-trust for firmware updates and prevents unauthorized code execution in production vehicles. |
| Automotive Thermal Rating | AEC-Q100 Grade 2 qualification (–40°C to +105°C junction) with thermal shutdown (TSHUT) monitoring - ensures reliable operation in under-hood and dashboard-mounted infotainment modules. |
Applications
| Navigation System | Digital Radio Platform |
|---|---|
Use Scenario: Real-time map rendering, voice-guided turn-by-turn navigation, and traffic-aware route recalculation in automotive head units. IC Role / Device Role / Timing Role: Main applications processor executing Linux OS, Qt-based UI framework, and navigation engine - synchronizing GPS, IMU, and cellular data streams via PCIe and UART interfaces. Use Value: 1.5 GHz Cortex-A15 + 512KB ECC RAM ensures sub-100ms UI response and zero-frame-drop map panning at 60 fps using GPU-accelerated OpenGL ES 2.0 rendering. | Use Scenario: AM/FM/RDS and HD Radio™ decoding with multi-band audio streaming and metadata display in premium vehicle audio systems. IC Role / Device Role / Timing Role: Baseband processor and audio subsystem controller - hosting ATL (Audio Tracking Logic), VCP (Viterbi Coprocessor), and McASP audio serial ports for low-jitter I2S/TDM audio transport. Use Value: Dedicated ATL/VCP hardware accelerates RDS decoding and HD Radio synchronization, reducing DSP load by >40% and enabling concurrent Bluetooth audio playback. |
| Rear-Seat Entertainment | ADAS Integration Hub |
Use Scenario: Dual-screen video playback (HDMI + LCD) with wireless screen mirroring, DRM-protected content, and multi-zone audio routing for rear passengers. IC Role / Device Role / Timing Role: Multimedia SoC managing HDMI encoder, VPE video pipeline, BB2D compositor, and eight McASP audio ports - coordinating video decode, audio decode, and display timing via display subsystem DMA engines. Use Value: Triple-video-pipeline display subsystem supports independent 1080p HDMI output and dual 720p LCD panels simultaneously with hardware color space conversion and gamma correction. | Use Scenario: Sensor fusion hub aggregating camera, radar, and ultrasonic inputs for driver assistance features like blind-spot detection and parking assist. IC Role / Device Role / Timing Role: Vision preprocessing node - offloading camera ISP functions (demosaic, noise reduction) to dual Cortex-M4 IPUs while feeding processed frames to A15/DSP for object detection. Use Value: Dual IPU architecture enables real-time 30fps camera stream processing at <5ms latency, freeing A15 core for neural network inference and CAN message arbitration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive infotainment applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DRA725BPL1ABCRQ1 | Same package and pinout; lacks second PCIe lane and one McASP module; lower speed grade (1.2 GHz A15 vs. 1.5 GHz) | Suitable for cost-optimized entry-level head units without dual-camera or high-bandwidth modem connectivity | Select when PCIe bandwidth and McASP count are non-critical and BOM cost reduction is prioritized over future scalability. |
| DRA746BPT1ABCRQ1 | Higher-performance variant: dual Cortex-A15 cores, dual C66x DSPs, 1MB L3 RAM, PCIe Gen3 support, and expanded IPU/GPU resources | Targeted at flagship digital cockpits requiring quad-display support, AI-based voice assistants, and full ADAS domain controller functionality | Choose when system requires >2x CPU throughput, hardware virtualization, or ISO 26262 ASIL-B compliance via dual-lockstep core configuration. |
Compared with DRA725BPL1ABCRQ1, the DRA726BPL1ABCRQ1 delivers higher compute headroom and PCIe flexibility for scalable infotainment; versus DRA746BPT1ABCRQ1, it offers proven AEC-Q100 qualification at lower power and cost, making it optimal for production-tier automotive platforms balancing performance and thermal envelope.
Availability
DRA726BPL1ABCRQ1 is available at Aetrix Electronics and suitable for automotive infotainment systems, digital radio platforms, and ADAS integration hubs requiring stable component supply across extended product lifecycles and rigorous environmental qualification.
Supply support for DRA726BPL1ABCRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and automotive technologies, with decades of leadership in automotive-grade SoCs and functional safety solutions.
The DRA726BPL1ABCRQ1 belongs to the Jacinto™6 Eco family - engineered specifically for cost-sensitive, thermally constrained automotive infotainment applications requiring AEC-Q100 qualification, multimedia acceleration, and seamless integration with legacy CAN and modern Ethernet vehicle networks.
FAQ
What is the maximum DDR3 data rate supported by the DRA726BPL1ABCRQ1?
The DRA726BPL1ABCRQ1 supports DDR3/DDR3L memory up to 1333 MT/s (667 MHz clock), with EMIF configured for single chip select up to 2GB capacity. This bandwidth sustains concurrent 1080p video decode, GPU rendering, and navigation data processing without memory bottlenecks in automotive head unit designs.
Does the DRA726BPL1ABCRQ1 include hardware cryptographic acceleration?
Yes, the DRA726BPL1ABCRQ1 integrates dedicated hardware accelerators for AES-128/256, SHA-1/256, DES/3DES, and RSA - enabling fast secure boot verification, encrypted firmware updates, and TLS offload in telematics and OTA update subsystems without taxing the Cortex-A15 or DSP cores.
Is the DRA726BPL1ABCRQ1 pin-compatible with other DRA72x devices?
Yes, the DRA726BPL1ABCRQ1 shares identical 760-pin FCBGA (ABC) packaging and pinout with DRA722, DRA724, and DRA725 variants - allowing PCB reuse across performance tiers and simplifying platform scalability for automotive OEMs developing multiple infotainment SKUs from a common hardware design.
What video output interfaces does the DRA726BPL1ABCRQ1 support?
The DRA726BPL1ABCRQ1 supports HDMI 1.4a and DVI 1.0 compliant output via its integrated encoder, plus three independent video pipelines driving LCD1/LCD2/LCD3 interfaces. It delivers full-HD (1920×1080p at 60 fps) with hardware scaling, blending, and color space conversion for multi-display automotive HMI systems.
How does the DRA726BPL1ABCRQ1 handle automotive safety and security requirements?
The DRA726BPL1ABCRQ1 meets AEC-Q100 Grade 2 qualification and includes JTAG lock, secure ROM boot, hardware crypto engines, firewalls, and silicon-revision 2.1 customer-programmable keys. While not ASIL-certified out-of-box, its security primitives enable implementation of ISO 26262-compliant secure boot and runtime attestation when combined with certified software stacks.
DRA726BPL1ABCRQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 760-BFBGA, FCBGA
- Series:
- DRA72x
- Packaging:
- Bulk
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A15
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 750MHz
- Co-Processors/DSP:
- ARM® Cortex®-M4, BB2D, C66x, GPU, IVA
- RAM Controllers:
- DDR3, DDR3L
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- HDMI, LCD
- Ethernet:
- 10/100Mbps (1), 10/100/1000Mbps (1)
- SATA:
- SATA
- USB:
- USB 2.0 (2), USB 3.0 (1)
- Voltage - I/O:
- 1.35V, 1.5V, 1.8V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Security Features:
- Cryptography, Debug Security, Device Identity, Isolation Firewalls, Secure Boot, Secure Storage, Software IP Protection
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 760-FCBGA (23x23)
- Additional Interfaces:
- 1-Wire®, CANbus, DMA, I2C, IrDA, McASP, MMC/SD/SDIO, PCIe, QSPI, UART, USB 3.0
DRA726BPL1ABCRQ1 FAQ
1.How can I place an order for DRA726BPL1ABCRQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DRA726BPL1ABCRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DRA726BPL1ABCRQ1 reliable?
The price and inventory of DRA726BPL1ABCRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DRA726BPL1ABCRQ1 is usually 5 days.
3.What payment methods are accepted for DRA726BPL1ABCRQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DRA726BPL1ABCRQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DRA726BPL1ABCRQ1?
DRA726BPL1ABCRQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DRA726BPL1ABCRQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DRA726BPL1ABCRQ1?
For technical support, including DRA726BPL1ABCRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DRA726BPL1ABCRQ1 requirements.
6.How does Aetrix verify that DRA726BPL1ABCRQ1 is sourced from the original manufacturer or authorized distributors?
All DRA726BPL1ABCRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DRA726BPL1ABCRQ1 meets industry standards.
7.What is the process for return or replacement of DRA726BPL1ABCRQ1?
All DRA726BPL1ABCRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DRA726BPL1ABCRQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DRA726BPL1ABCRQ1 part is unused and in its original packaging.
Return procedure for DRA726BPL1ABCRQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DRA726BPL1ABCRQ1 Tags
-
AT91SAM9260B-CU-999
Microchip Technology
-
AT91SAM9G25-CU
Microchip Technology
-
ATSAMA5D27C-CU
Microchip Technology
-
AT91SAM9X35-CU
Microchip Technology
-
AT91SAM9X25-CU
Microchip Technology
-
MCIMX6Y2CVM08AB
NXP Semiconductors
.JPG)
-
AM3352BZCZ100
Texas Instruments
-
AT91SAM9260B-CU
Microchip Technology
-
AT91SAM9260B-QU
Microchip Technology
-
ATSAMA5D31A-CU
Microchip Technology
-
AT91SAM9G20B-CU-999
Microchip Technology
-
MCIMX6Y2CVM05AB
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
