Analog Devices Inc./Maxim Integrated DS1005M-60+

Overview

DS1005M-60+ from Maxim Integrated (formerly Dallas Semiconductor) is a 5-tap all-silicon delay line with fixed tap delays of 12 ns, 24 ns, 36 ns, 48 ns, and 60 ns; TTL/CMOS-compatible input/output; ±2 ns or ±3% delay tolerance; and designed for precise edge-aligned timing in digital signal conditioning. It operates at 5.0 V ±5%, drives up to ten 74LS loads per tap, and is used in clock skew correction and pulse-width modulation circuits.

For engineers reviewing the DS1005M-60+ datasheet, DS1005M-60+ pinout, DS1005M-60+ application, or DS1005M-60+ equivalent, key selection considerations include leading/trailing edge accuracy, 8-pin DIP package compatibility, tap delay stability over 0°C to 70°C, and load-driving capability per output.

Technical Context

The DS1005M-60+ implements a monolithic silicon delay structure-not RC or analog-based-ensuring deterministic propagation delay across all five taps. Each tap reproduces logic level with matched tPLH and tPHL, and delay variation is unidirectional with temperature/voltage shifts.

It uses standard CMOS process technology with 5.0 V supply, 10 pF typical input capacitance, and active current draw of 40–70 mA. Input thresholds meet TTL/CMOS levels (VIH ≥ 2.2 V, VIL ≤ 0.8 V), and outputs are specified at 1.5 V switching threshold for timing measurement consistency.

Key Specifications

Pinout & Package

DS1005M-60+ is supplied in an 8-pin DIP (300-mil) package with gull-wing leads, auto-insertable and wave-solder compatible. Pin 1 is IN; pins 2–3 and 5–8 are TAP 2, TAP 4, GND, VCC, TAP 1, TAP 3, TAP 5 respectively; no NC pins present in this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 5-tap fixed-delay line applications.

Compared with DS1005-60+ and DS1005S-60+, the DS1005M-60+ offers the smallest footprint among variants while retaining identical delay accuracy, edge fidelity, and load drive-making it optimal for cost-sensitive, auto-insertable commercial designs.

Availability

DS1005M-60+ is available at Aetrix Electronics and suitable for digital test equipment, industrial motion controllers, FPGA timing alignment, and embedded signal conditioning applications requiring stable component supply and long-term obsolescence management.

Supply support for DS1005M-60+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (acquired by Analog Devices in 2021) is a U.S.-based semiconductor company specializing in precision analog, mixed-signal, and timing solutions.

The DS1005M-60+ belongs to Maxim's legacy silicon delay line product line, engineered for deterministic, low-jitter digital timing in commercial-grade systems where hybrid delay lines were previously used.

FAQ

What is the exact delay value for TAP 3 on the DS1005M-60+?

The DS1005M-60+ provides a fixed 36 ns delay at TAP 3, measured as tPLH and tPHL from the 1.5 V input transition point to the corresponding 1.5 V output transition point. This value is guaranteed across 0°C to 70°C and 4.75 V to 5.25 V supply, with tolerance of ±2 ns or ±3%, whichever is greater. The DS1005M-60+ maintains identical delay accuracy on both rising and falling edges.

Does the DS1005M-60+ require external decoupling capacitors?

Yes, the DS1005M-60+ requires a 0.1 µF ceramic decoupling capacitor placed as close as possible to the VCC and GND pins. This minimizes supply noise-induced delay variation and ensures stable operation under fast-switching load conditions. The DS1005M-60+ datasheet specifies that failure to provide proper decoupling may degrade delay accuracy beyond the ±2 ns/±3% specification.

Can the DS1005M-60+ drive 74ACT logic loads directly?

The DS1005M-60+ can drive 74ACT loads only under limited conditions: its IOL = 12 mA and IOH = –1 mA meet 74ACT input requirements at VCC = 5 V, but margin shrinks below 4.75 V. For robust 74ACT interfacing across full voltage/temp range, a buffer stage is recommended. The DS1005M-60+ is fully specified for 74LS loads, not 74ACT.

Is the DS1005M-60+ pin-compatible with older hybrid delay lines?

The DS1005M-60+ is not pin-compatible with legacy hybrid delay lines due to its 8-pin DIP pinout (IN, TAP2, TAP4, GND, VCC, TAP1, TAP3, TAP5), which differs from standard 14-pin hybrid layouts. However, the DS1005-60+ variant retains hybrid lead configuration for drop-in replacement. The DS1005M-60+ requires PCB redesign for migration from hybrid parts.

What is the maximum input pulse width the DS1005M-60+ supports?

The DS1005M-60+ does not specify a maximum input pulse width; instead, minimum pulse width is defined as 40% of TAP5 tPLH (i.e., ≥24 ns for DS1005M-60+). Pulses wider than this are supported, but accuracy becomes sensitive to layout, decoupling, and signal integrity. The DS1005M-60+ datasheet confirms pulse width and duty cycle may be exceeded, though timing fidelity remains application-dependent.