Analog Devices Inc./Maxim Integrated DS1013M-167
- Part No.:
- DS1013M-167
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
DS1013M-167.pdf
- Description:
- IC DELAY LINE 167NS 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:2,606
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS1013M-167 from Dallas Semiconductor (now Maxim Integrated) is a 3-channel all-silicon logic delay line in an 8-pin DIP package, delivering three independent buffered 167 ns delays with ±5% tolerance, TTL/CMOS compatibility, and leading/trailing edge accuracy for timing alignment in digital signal paths. It operates at 5 V, supports 10 LS-load drive per output, and targets applications requiring precise inter-channel skew control.
For engineers reviewing the DS1013M-167 datasheet, DS1013M-167 pinout, DS1013M-167 application, or DS1013M-167 equivalent, key selection criteria include confirmed 167 ns nominal delay per channel, ±5% delay tolerance (per Table 1 footnote **), 8-pin DIP mechanical footprint, 5 V supply operation, and verified 74LS load drive capability - all validated against Dallas Semiconductor's official DS1013 family documentation.
Technical Context
The DS1013M-167 implements fixed, non-programmable propagation delays using silicon-based delay elements with internal buffering, ensuring matched tPLH and tPHL across all three channels. Its architecture guarantees equal precision on both rising and falling edges, with unidirectional delay drift over temperature and voltage.
Designed as a drop-in replacement for hybrid delay lines, it eliminates trimming and aging issues while maintaining compatibility with legacy 300-mil DIP layouts. Delay stability is specified over 0°C to +70°C and 4.75 V to 5.25 V, with delay shift bounded by ±1.5 ns or ±3% under combined temp/voltage variation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Nominal Delay | 167 ns per output - fixed, identical delay on IN1→OUT1, IN2→OUT2, IN3→OUT3 |
| Delay Tolerance | ±5% - applies to delays ≥150 ns (per Table 1 ** footnote) |
| Supply Voltage | 4.75 V to 5.25 V - ensures stable delay performance within standard TTL/CMOS 5 V rail |
| Output Drive | 12 mA sink / –1 mA source - supports direct interface to 10 × 74LS loads |
| Operating Temp | 0°C to +70°C - commercial-grade range suitable for industrial control and instrumentation |
| Input Logic Levels | VIH ≥ 2.2 V, VIL ≤ 0.8 V - fully compatible with TTL and CMOS logic families |
| Edge Accuracy | Matched tPLH/tPHL - enables precise pulse width preservation and skew-critical timing alignment |
Pinout & Package
DS1013M-167 uses an 8-pin plastic DIP (300-mil) package with 0.3 inch width and standard through-hole mounting. Pin 1 is marked with a notch or dot; pins are numbered counter-clockwise from top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (IN1) | Input Channel 1 | Accepts TTL/CMOS logic signal; drives internal delay path 1 |
| 2 (NC) | No Connection | Unbonded die pad - must remain floating, not tied to GND or VCC |
| 3 (NC) | No Connection | Unbonded die pad - no electrical function; PCB trace may be omitted |
| 4 (IN2) | Input Channel 2 | Independent input for second 167 ns delay path |
| 5 (IN3) | Input Channel 3 | Independent input for third 167 ns delay path |
| 6 (NC) | No Connection | Unbonded die pad - no routing required |
| 7 (GND) | Ground Reference | Primary return path for supply and signal integrity; requires low-impedance connection |
| 8 (VCC) | Power Supply | +5 V DC supply input; bypassing with 0.1 µF ceramic capacitor near pin recommended |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon construction | Eliminates aging, thermal drift, and calibration drift inherent in hybrid/ceramic delay lines |
| Three independent buffered delays | Enables simultaneous delay of three asynchronous signals without crosstalk or loading interaction |
| Leading and trailing edge accuracy | Preserves pulse width integrity - critical for clock distribution, strobe alignment, and data eye positioning |
| TTL/CMOS-compatible I/O | Direct interfacing with 74LS, 74HC, and microcontroller GPIO without level-shifting circuitry |
| Auto-insertable 8-pin DIP | Supports high-volume through-hole assembly and rework-friendly socketing |
Applications
| Digital Test Equipment | Industrial PLC Timing Modules |
|---|---|
Use Scenario: Aligning stimulus and response capture windows in automated test systems to resolve setup/hold timing margins. IC Role / Device Role / Timing Role: Provides deterministic, matched delay for synchronizing trigger and sampling clocks across multiple channels. Use Value: Enables sub-nanosecond skew control between parallel test channels, improving measurement repeatability and fault coverage. | Use Scenario: Introducing calibrated dead time between relay driver enable and feedback confirmation in safety-critical ladder logic execution. IC Role / Device Role / Timing Role: Acts as a hardware-enforced delay element to prevent race conditions during I/O state transitions. Use Value: Guarantees minimum 167 ns assertion time before feedback validation, eliminating false trip events in real-time control loops. |
| Video Signal Skew Compensation | Legacy Bus Interface Timing |
Use Scenario: Compensating trace-length mismatch between RGB data lanes in analog video DAC interfaces (e.g., VGA, SDI). IC Role / Device Role / Timing Role: Equalizes propagation delay across parallel video data paths to maintain pixel alignment at the display interface. Use Value: Prevents visible color fringing or horizontal jitter by matching tPLH/tPHL across all three channels within ±5%. | Use Scenario: Matching address/data valid timing in 8-bit microprocessor bus expansions (e.g., Z80, 8085) where peripheral access latency must exceed CPU cycle minimums. IC Role / Device Role / Timing Role: Inserts fixed delay on WAIT or READY assertion to meet memory-mapped I/O timing requirements. Use Value: Eliminates need for external RC networks or programmable logic, reducing BOM count and layout complexity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fixed-delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1013S-167 | Same 167 ns delay and specs, but in 16-pin SOIC package - no pin compatibility with DS1013M-167 | Requires surface-mount PCB redesign; unsuitable for through-hole legacy systems | Select only when board space constraints justify SMT migration and requalification |
| MAX5517EPA+ | Programmable 8-tap delay (1–256 ns steps), ±1 ns resolution, but single-channel and higher power | Used where dynamic delay adjustment is required; not a fixed-delay substitute | Choose only if design demands runtime configurability - not for static 167 ns alignment |
Compared with DS1013S-167 and MAX5517EPA+, the DS1013M-167 delivers guaranteed 167 ns fixed delay in a proven, low-cost, auto-insertable DIP format - ideal for cost-sensitive, volume-manufactured systems where pinout stability and assembly simplicity outweigh programmability or miniaturization needs.
Availability
DS1013M-167 is available at Aetrix Electronics and suitable for digital test equipment, industrial PLC timing modules, video signal skew compensation, and legacy bus interface timing requiring stable component supply and long-term obsolescence management.
Supply support for DS1013M-167 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Dallas Semiconductor, acquired by Maxim Integrated in 2001, specialized in precision analog, timing, and secure memory ICs for industrial and embedded applications.
The DS1013 series was designed specifically to replace aging hybrid delay lines with reliable, low-cost, all-silicon alternatives for fixed-timing applications in test, control, and interface systems.
FAQ
What is the exact delay value and tolerance for DS1013M-167?
The DS1013M-167 provides a nominal delay of 167 ns on all three outputs (IN1→OUT1, IN2→OUT2, IN3→OUT3), with a tolerance of ±5% as specified in Table 1 footnote ** of the Dallas Semiconductor DS1013 datasheet. This tolerance applies because 167 ns exceeds the 150 ns threshold where accuracy shifts from ±2 ns to percentage-based error.
Is DS1013M-167 pin-compatible with other DS1013 variants like DS1013-167 in 14-pin DIP?
No, DS1013M-167 is not pin-compatible with the 14-pin DIP version. The "M" suffix denotes the 8-pin DIP package with dedicated IN1/IN2/IN3 inputs and NC pins, whereas the 14-pin variant has different pin spacing and assignment. Board layout must match the 300-mil 8-pin DIP footprint for DS1013M-167.
Can DS1013M-167 drive standard TTL loads directly?
Yes, DS1013M-167 can drive up to 10 × 74LS loads per output, as confirmed in the device description and DC electrical characteristics. Its IOL = 12 mA and IOH = –1 mA meet 74LS input current requirements, enabling direct connection without buffer amplification in most legacy digital systems.
Does DS1013M-167 support operation outside the 0°C to +70°C range?
No - DS1013M-167 is rated for commercial temperature operation only (0°C to +70°C), per the Absolute Maximum Ratings table. Extended temperature versions (e.g., DS1013M-167I) exist but require separate ordering; the base DS1013M-167 part number does not guarantee functionality beyond this range.
How does DS1013M-167 handle rising vs. falling edge delays?
DS1013M-167 reproduces both rising (tPLH) and falling (tPHL) edges with equal precision and matched delay values, as explicitly stated in the Description section and Timing Diagram notes. This ensures consistent pulse width preservation - a core design requirement distinguishing it from basic RC or gate-based delay circuits.
DS1013M-167 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 167ns
- Tap Increment:
- -
- Available Total Delays:
- 167ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
DS1013M-167 FAQ
1.How can I place an order for DS1013M-167 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1013M-167 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1013M-167 reliable?
The price and inventory of DS1013M-167 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1013M-167 is usually 5 days.
3.What payment methods are accepted for DS1013M-167?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1013M-167 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1013M-167?
DS1013M-167 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1013M-167 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1013M-167?
For technical support, including DS1013M-167 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1013M-167 requirements.
6.How does Aetrix verify that DS1013M-167 is sourced from the original manufacturer or authorized distributors?
All DS1013M-167 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1013M-167 meets industry standards.
7.What is the process for return or replacement of DS1013M-167?
All DS1013M-167 units undergo pre-shipment inspection (PSI). If there is an issue with DS1013M-167, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1013M-167 part is unused and in its original packaging.
Return procedure for DS1013M-167:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1013M-167 Tags

-
LTC6994CS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994CDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-1#TRPBF
Analog Devices Inc.

-
LTC6994IDCB-1#TRMPBF
Analog Devices Inc.

-
LTC6994IS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRPBF
Analog Devices Inc.

-
LTC6994HS6-1#TRMPBF
Analog Devices Inc.

-
LTC6994HS6-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-2#TRMPBF
Analog Devices Inc.

-
LTC6994HDCB-1#TRMPBF
Analog Devices Inc.

-
DS1124U-25+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

