Analog Devices Inc./Maxim Integrated DS1013M-200+
- Part No.:
- DS1013M-200+
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
DS1013M-200+.pdf
- Description:
- IC DELAY LINE 200NS 8DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS1013M-200+ from Dallas Semiconductor (now Maxim Integrated) is a 3-channel all-silicon logic delay line in an 8-pin DIP package, delivering three independent 200 ns nominal delays (tPLH/tPHL) with ±5% tolerance, TTL/CMOS-compatible I/O, and operation over 0°C to 70°C - used for edge-aligned timing correction in digital test equipment and high-speed bus synchronization.
For engineers reviewing the DS1013M-200+ datasheet, DS1013M-200+ pinout, DS1013M-200+ application, or DS1013M-200+ equivalent, key selection criteria include guaranteed 200 ns delay accuracy across temperature/voltage, leading/trailing edge matching, 10 LS-load drive capability, and compatibility with legacy hybrid delay line footprints.
Technical Context
The DS1013M-200+ implements three identical, buffered delay paths using monolithic CMOS silicon - eliminating hybrid construction artifacts like thermal drift and parasitic coupling. Each channel reproduces both rising and falling edges with matched tPLH and tPHL values at 200 ns ±5%, verified under VCC = 5.0V ±5% and TA = 25°C.
It operates with standard TTL/CMOS input thresholds (VIH ≥ 2.2 V, VIL ≤ 0.8 V), drives up to 10 74LS loads per output, and maintains stable delay performance across supply voltage (4.75–5.25 V) and ambient temperature (0–70°C), with unidirectional delay shift behavior across operating conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 200 ns nominal (tPLH/tPHL); ±5% tolerance over full temp/voltage range |
| Supply voltage | 4.75 V to 5.25 V - supports standard +5 V logic rails with 5% regulation margin |
| Input compatibility | TTL/CMOS - accepts VIH ≥ 2.2 V, VIL ≤ 0.8 V; no level-shifting required |
| Output drive | 12 mA sink / –1 mA source - sufficient for 10 × 74LS inputs without buffering |
| Operating temp | 0°C to 70°C - commercial-grade rating suitable for benchtop and industrial control systems |
| Input capacitance | 5–10 pF - low loading preserves signal integrity on high-speed logic lines |
Pinout & Package
DS1013M-200+ uses an 8-pin plastic DIP (300-mil width) with gull-wing leads. Pin 1 is IN1; pins 2, 3, and 6 are NC; pin 4 is IN2; pin 5 is IN3; pin 7 is GND; pin 8 is VCC; outputs OUT1, OUT2, OUT3 are on pins 11, 12, 13 of the 14-pin variant but mapped to pins 14, 15, 16 in SOIC - not present in this 8-pin version. Per datasheet, DS1013M is the 8-pin DIP variant with only IN1, IN2, IN3, GND, VCC, and three NC pins - no output pins on this package.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN 1 | Input channel 1 | Accepts TTL/CMOS logic signal; delays rising/falling edges by 200 ns |
| IN 2 | Input channel 2 | Independent input path; identical 200 ns delay as IN1 |
| IN 3 | Input channel 3 | Third isolated delay path; no crosstalk between channels |
| GND | Ground reference | Common return for all internal logic and output drivers |
| VCC | Power supply | +5 V supply pin; requires local 0.1 µF ceramic decoupling |
| NC (pins 2,3,6) | No connection | Not bonded internally; must remain unconnected on PCB |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon construction | Eliminates hybrid delay line reliability risks (e.g., wire bond fatigue, thermal mismatch) |
| Edge-matched delay | tPLH and tPHL both 200 ns ±5% - enables precise pulse width preservation |
| Three independent channels | No inter-channel skew; each input/output pair operates autonomously |
| Low-power CMOS | ICC = 40–70 mA typical - reduces board-level heat and power supply burden |
| Auto-insertable package | Standard 8-pin DIP footprint - compatible with automated through-hole assembly |
Applications
| Digital Test Equipment | High-Speed Bus Synchronization |
|---|---|
Use Scenario: Aligning trigger signals across multiple oscilloscope channels or logic analyzer inputs. IC Role / Device Role / Timing Role: Provides deterministic 200 ns offset to match propagation delays in parallel measurement paths. Use Value: Enables simultaneous sampling of multi-channel digital waveforms with sub-nanosecond alignment consistency. | Use Scenario: Compensating for trace-length mismatch between clock and data lines in LVDS or TTL bus interfaces. IC Role / Device Role / Timing Role: Introduces calibrated delay on clock path to meet setup/hold timing windows at receivers. Use Value: Eliminates need for PCB trace tuning; achieves timing closure without layout iteration. |
| Programmable Logic Timing Calibration | Legacy System Interfacing |
Use Scenario: Adjusting strobe timing between FPGA-configured peripherals and fixed-function ASICs. IC Role / Device Role / Timing Role: Acts as programmable delay element in glue logic between heterogeneous logic families. Use Value: Resolves timing violations caused by differing propagation characteristics across vendor IP blocks. | Use Scenario: Replacing obsolete hybrid delay lines (e.g., MDA-200) in fielded military or telecom hardware. IC Role / Device Role / Timing Role: Drop-in silicon replacement preserving original 8-pin DIP footprint and electrical interface. Use Value: Restores supply chain continuity while improving long-term reliability and temperature stability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar logic delay line applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1013S-200+ | 16-pin SOIC package; same 200 ns delay, ±5% tolerance, and electrical specs | Requires surface-mount assembly; saves board area vs. through-hole DIP | Select when PCB space is constrained and SMT process is available |
| MC100EP195DG | Differential ECL output; 200 ps typical delay resolution; 3.3 V supply; higher speed but incompatible voltage domain | Used in RF/datacom clock distribution, not TTL/CMOS logic timing | Select only for high-speed differential signaling; not a functional substitute for DS1013M-200+ |
Compared with DS1013S-200+, the DS1013M-200+ offers identical timing performance in a through-hole package for legacy assembly, while MC100EP195DG targets entirely different voltage domains and signal integrity requirements - neither is pin-compatible, but DS1013S-200+ serves as a direct form-factor alternative.
Availability
DS1013M-200+ is available at Aetrix Electronics and suitable for digital test equipment, high-speed bus synchronization, and legacy system interfacing requiring stable component supply and long-term obsolescence mitigation.
Supply support for DS1013M-200+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Dallas Semiconductor, now part of Maxim Integrated (acquired 2001), specialized in precision analog, timing, and secure memory ICs for industrial and communications applications.
The DS1013 series was designed as a monolithic silicon replacement for hybrid delay lines - targeting cost-sensitive, high-reliability digital timing applications where stability, edge fidelity, and drop-in upgradeability mattered.
FAQ
What is the actual delay tolerance of DS1013M-200+ across temperature and voltage?
The DS1013M-200+ has a nominal 200 ns delay with ±5% tolerance over the full operating range (0°C to 70°C, VCC = 4.75 V to 5.25 V). This includes ±1.5 ns or ±3% additional shift due to combined temp/voltage variation, per datasheet Note 5. DS1013M-200+ does not meet the tighter ±2 ns spec reserved for -10 to -60 variants.
Does DS1013M-200+ support both rising and falling edge delays equally?
Yes. DS1013M-200+ guarantees matched tPLH (rising edge) and tPHL (falling edge) delays of 200 ns ±5%, enabling precise pulse width retention. This edge-matching is confirmed in the AC Electrical Characteristics table and Timing Diagram Figure 2 of the official datasheet.
Can DS1013M-200+ drive standard TTL loads directly?
Yes. DS1013M-200+ can drive up to 10 × 74LS loads per output (IOL = 12 mA min, IOH = –1 mA min), meeting standard TTL fan-out requirements without external buffers. Its VCC = 5 V operation and TTL-compatible input thresholds ensure seamless integration.
Is DS1013M-200+ pin-compatible with older hybrid delay lines?
No - DS1013M-200+ uses an 8-pin DIP package with only five active pins (IN1/IN2/IN3/GND/VCC); it is not pin-compatible with 14-pin hybrid equivalents. The 14-pin DS1013 variant is pin-compatible, but DS1013M-200+ is a space-optimized variant with NC pins replacing outputs.
What is the maximum input pulse width supported by DS1013M-200+?
DS1013M-200+ supports input pulses with width ≥100% of tPLH (i.e., ≥200 ns), per AC Electrical Characteristics. The datasheet specifies tWI ≥ 200 ns minimum; shorter pulses may cause timing uncertainty or incomplete propagation through the delay path.
DS1013M-200+ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 200ns
- Tap Increment:
- -
- Available Total Delays:
- 200ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
DS1013M-200+ FAQ
1.How can I place an order for DS1013M-200+ through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1013M-200+ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1013M-200+ reliable?
The price and inventory of DS1013M-200+ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1013M-200+ is usually 5 days.
3.What payment methods are accepted for DS1013M-200+?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1013M-200+ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1013M-200+?
DS1013M-200+ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1013M-200+ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1013M-200+?
For technical support, including DS1013M-200+ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1013M-200+ requirements.
6.How does Aetrix verify that DS1013M-200+ is sourced from the original manufacturer or authorized distributors?
All DS1013M-200+ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1013M-200+ meets industry standards.
7.What is the process for return or replacement of DS1013M-200+?
All DS1013M-200+ units undergo pre-shipment inspection (PSI). If there is an issue with DS1013M-200+, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1013M-200+ part is unused and in its original packaging.
Return procedure for DS1013M-200+:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1013M-200+ Tags

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