Analog Devices Inc./Maxim Integrated DS1013M-75+

Overview

DS1013M-75+ from Maxim Integrated (formerly Dallas Semiconductor) is a 3-channel all-silicon logic delay line in an 8-pin DIP package, delivering precisely matched 75 ns ±3% propagation delays on all three outputs (tPLH/tPHL), TTL/CMOS-compatible input/output levels, and operation at 5V ±5%. It reproduces both rising and falling edges with equal accuracy and drives up to 10 LS-TTL loads per output - used in digital timing alignment, clock skew correction, and pulse width adjustment in test instrumentation.

For engineers reviewing the DS1013M-75+ datasheet, DS1013M-75+ pinout, DS1013M-75+ application, or DS1013M-75+ equivalent, key selection considerations include guaranteed ±3% delay tolerance at 75 ns, edge-matched dual-edge delay fidelity, 8-pin DIP footprint compatibility with legacy hybrid delay lines, and DC/AC specs validated across 0°C to 70°C at VCC = 5.0V ±5%.

Technical Context

The DS1013M-75+ implements three independent buffered delay paths using low-power CMOS logic, each with identical 75 ns nominal delay (tPLH = tPHL = 75 ns). Delay accuracy is specified as ±3% over temperature (0°C to 70°C) and supply voltage (4.75V–5.25V), with unidirectional delay drift across operating conditions.

All inputs accept TTL/CMOS logic levels (VIH ≥ 2.2 V, VIL ≤ 0.8 V), and outputs drive 10 LS-TTL loads while maintaining VOH ≥ 4.0 V and VOL ≤ 0.5 V. Input rise/fall times are specified ≤3.0 ns, and pulse width must exceed 100% of tPLH (i.e., ≥75 ns) for valid timing operation.

Key Specifications

Pinout & Package

DS1013M-75+ uses an 8-pin plastic DIP (300-mil) package with gull-wing leads, auto-insertable and compatible with vapor phase, IR, and wave soldering processes.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar logic delay line applications.

Compared with DS1013-75+ and MC100ELT20DG, the DS1013M-75+ uniquely delivers factory-trimmed, edge-matched 75 ns delay in an 8-pin DIP - offering optimal balance of precision, footprint, and drop-in replaceability for commercial instrumentation timing paths.

Availability

DS1013M-75+ is available at Aetrix Electronics and suitable for digital test equipment, industrial PLC timing modules, and high-speed data acquisition systems requiring stable component supply and long-term obsolescence mitigation.

Supply support for DS1013M-75+ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (acquired by Analog Devices in 2021) designs precision analog, mixed-signal, and timing ICs for industrial, communications, and computing applications.

The DS1013M-75+ belongs to Maxim's legacy silicon delay line product line, engineered specifically for deterministic, low-jitter digital signal alignment in commercial-grade test and control systems.

FAQ

What is the guaranteed delay tolerance for DS1013M-75+ across temperature and voltage?

The DS1013M-75+ guarantees ±3% delay tolerance over the full operating range of 0°C to 70°C and VCC = 4.75 V to 5.25 V. This corresponds to a 75 ns nominal delay varying between 72.75 ns and 77.25 ns. The specification accounts for combined temperature and voltage effects, with all three outputs drifting unidirectionally - meaning if one output slows, the others slow proportionally.

Does DS1013M-75+ support both rising and falling edge delays equally?

Yes, DS1013M-75+ reproduces both leading (tPLH) and trailing (tPHL) edges with identical 75 ns ±3% delay. The device is explicitly characterized for edge-matched performance, ensuring pulse width preservation and symmetry - critical for applications like clock deskewing and pulse shaping where duty cycle integrity matters.

Can DS1013M-75+ drive standard TTL loads directly?

Yes, DS1013M-75+ can drive up to 10 LS-TTL loads per output, with IOL = 12.0 mA (min) at VOL = 0.5 V and IOH = –1.0 mA (min) at VOH = 4.0 V. Its output structure meets standard TTL interface requirements without external buffering, making it suitable for direct connection to 74LSxx and 74Fxx logic families.

What is the maximum input pulse width requirement for reliable DS1013M-75+ operation?

DS1013M-75+ requires input pulse width (tWI) to be ≥100% of tPLH - i.e., ≥75 ns - to ensure accurate delay reproduction. Shorter pulses may cause incomplete propagation or edge distortion. The device also specifies maximum input rise/fall times of 3.0 ns to maintain timing fidelity and minimize jitter accumulation.

Is DS1013M-75+ pin-compatible with hybrid delay line replacements?

No, DS1013M-75+ is not pin-compatible with hybrid delay lines. It uses an 8-pin DIP configuration with multiple NC pins, whereas hybrid equivalents typically use 14-pin DIP footprints. For true pin-compatible replacement, DS1013-75+ (14-pin DIP) is the designated variant - DS1013M-75+ prioritizes board area reduction over mechanical interchangeability.