Analog Devices Inc./Maxim Integrated DS1013S-10
- Part No.:
- DS1013S-10
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
DS1013S-10.pdf
- Description:
- IC DELAY LINE 10NS 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS1013S-10 from Dallas Semiconductor (now Maxim Integrated) is a 3-channel all-silicon logic delay line in 16-pin SOIC package, delivering precise 10 ns fixed delay on each of three independent buffered outputs with ±2 ns tolerance over 0°C–70°C and 4.75V–5.25V supply, used for edge-aligned timing control in high-speed digital test and synchronization circuits.
For engineers reviewing the DS1013S-10 datasheet, DS1013S-10 pinout, DS1013S-10 application, or DS1013S-10 equivalent, key selection criteria include guaranteed leading/trailing edge accuracy, TTL/CMOS compatibility, 10 LS-load drive capability per output, and availability in surface-mount SOIC for space-constrained PCB layouts.
Technical Context
The DS1013S-10 implements three identical, fully buffered delay paths using low-power CMOS circuitry, each reproducing input logic state after a fixed 10 ns propagation delay measured at 1.5 V crossing point on both rising (tPLH) and falling (tPHL) edges. Delay stability is maintained across voltage (±5% VCC) and temperature (0°C to 70°C) variations.
All three outputs track unidirectionally under environmental stress-i.e., if one output slows due to temperature rise, all others slow proportionally-enabling predictable skew management in multi-tap timing applications without inter-channel calibration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Delay per output | 10 ns nominal, ±2 ns absolute tolerance (0°C–70°C, 4.75V–5.25V) |
| Input compatibility | TTL/CMOS logic levels: VIH ≥ 2.2 V, VIL ≤ 0.8 V |
| Output drive | 12 mA sink / –1 mA source, supports up to 10 × 74LS loads |
| Supply voltage | 4.75 V to 5.25 V; active current 40–70 mA typical |
| Input capacitance | 5–10 pF; minimal loading on upstream drivers |
| Operating temperature | 0°C to +70°C ambient; storage up to +125°C |
Pinout & Package
DS1013S-10 uses a 16-pin SOIC (300-mil) package with exposed pad not electrically connected. Pin 1 is IN1; pins 2–3 and 5–6 are NC; pin 4 is IN2; pin 5 is IN3; pin 7 is GND; pin 8 is NC; pins 9–10 are NC; pin 11 is OUT3; pin 12 is OUT2; pin 13 is OUT1; pin 14 is VCC; pins 15–16 are NC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | IN1 | Primary logic input for first delay channel |
| 4 | IN2 | Logic input for second independent delay channel |
| 5 | IN3 | Logic input for third independent delay channel |
| 7 | GND | Digital ground reference for all internal circuitry |
| 11 | OUT3 | Buffered 10 ns delayed output corresponding to IN3 |
| 12 | OUT2 | Buffered 10 ns delayed output corresponding to IN2 |
| 13 | OUT1 | Buffered 10 ns delayed output corresponding to IN1 |
| 14 | VCC | +5 V power supply; decoupling capacitor required at pin |
Key Features
| Feature | Design Value |
|---|---|
| Triple independent delay paths | Three isolated 10 ns delay channels share one die but do not interact electrically-enabling simultaneous timing alignment of multiple signals without crosstalk |
| Edge-accurate buffering | Both tPLH and tPHL specified identically at ±2 ns, ensuring matched rise/fall delay for pulse-width preservation |
| Low-power CMOS design | 40–70 mA ICC enables use in thermally constrained systems without forced cooling |
| Standard SOIC footprint | 16-pin 300-mil SOIC allows drop-in replacement of hybrid delay modules while reducing board area by >50% vs. 14-pin DIP |
Applications
| High-Speed Logic Test Equipment | Digital Signal Synchronization |
|---|---|
Use Scenario: Generating precisely offset clock or strobe signals for boundary-scan controller timing validation. IC Role / Device Role / Timing Role: DS1013S-10 provides deterministic 10 ns skew between parallel data capture clocks to verify setup/hold margins. Use Value: Eliminates need for discrete RC networks or FPGA-based delay generation, improving repeatability and reducing jitter-induced measurement error. | Use Scenario: Aligning asynchronous data streams from multiple ADCs before multiplexing into a common bus. IC Role / Device Role / Timing Role: DS1013S-10 delays selected channel enable signals to match propagation latency across signal paths. Use Value: Achieves sub-nanosecond inter-channel skew control without custom layout or trimming, enabling coherent sampling at >100 MSPS. |
| Programmable Logic Interface Timing | Industrial Control Pulse Shaping |
Use Scenario: Introducing controlled delay between FPGA configuration load signal and peripheral reset assertion. IC Role / Device Role / Timing Role: DS1013S-10 acts as a fixed-latency buffer to enforce minimum reset deassertion hold time after configuration completes. Use Value: Guarantees reliable initialization sequence without modifying HDL code or adding state-machine cycles. | Use Scenario: Extending pulse width of PLC output triggers driving solenoid valves with mechanical response lag. IC Role / Device Role / Timing Role: DS1013S-10 delays the trailing edge of control pulses to maintain actuator energization for exact 10 ns longer than input duration. Use Value: Compensates for valve coil inductance without external RC components, improving cycle-to-cycle repeatability in motion control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fixed-delay logic applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1013M-10 | Same 10 ns delay, 8-pin DIP package; no NC pins; smaller footprint but through-hole only | Preferred for prototyping or legacy through-hole boards where reflow compatibility is not required | Select DS1013M-10 when manual assembly or socketing is needed; DS1013S-10 is optimal for automated SMT lines. |
| MAX9992ETE+T | Single-output 10 ns delay, 16-pin TQFN; higher drive strength (24 mA), wider temp range (–40°C to +85°C) | Suitable for industrial environments requiring extended temperature operation and higher noise immunity | Choose MAX9992ETE+T when single-channel precision and extended reliability outweigh triple-channel integration. |
Compared with DS1013M-10 and MAX9992ETE+T, the DS1013S-10 uniquely delivers three synchronized 10 ns delays in a surface-mount package with proven 0°C–70°C stability and LS-load compatibility-making it optimal for cost-sensitive, space-constrained digital test fixtures requiring multi-signal alignment.
Availability
DS1013S-10 is available at Aetrix Electronics and suitable for high-speed logic test equipment, digital signal synchronization, and programmable logic interface timing requiring stable component supply and long-term obsolescence management.
Supply support for DS1013S-10 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Dallas Semiconductor, now part of Maxim Integrated (Analog Devices), specialized in precision timing, memory, and mixed-signal ICs for industrial and communications infrastructure.
The DS1013 series was designed as an all-silicon replacement for hybrid delay lines, targeting digital test, instrumentation, and synchronization systems needing repeatable, low-skew fixed delays without custom tuning.
FAQ
What is the guaranteed delay accuracy of the DS1013S-10 across its operating temperature range?
The DS1013S-10 guarantees ±2 ns delay accuracy for all three outputs over the full 0°C to +70°C operating temperature range and 4.75 V to 5.25 V supply voltage, as confirmed in the AC Electrical Characteristics table and Notes section of the official datasheet. This applies to both tPLH and tPHL measurements at the 1.5 V threshold level.
Does the DS1013S-10 support both rising and falling edge delay matching?
Yes, the DS1013S-10 is explicitly characterized for equal precision on both edges: tPLH (rising) and tPHL (falling) are identical at 10 ns ±2 ns. The datasheet confirms "leading and trailing edge accuracy" as a core feature, and Figure 2 (Timing Diagram) illustrates matched delay behavior for both transitions.
Can the DS1013S-10 drive standard TTL loads directly?
Yes, each output of the DS1013S-10 can drive up to 10 × 74LS loads, as stated in the Description section and verified by IOL = 12 mA (min) and IOH = –1 mA (min) in the DC Electrical Characteristics table. Its TTL/CMOS-compatible input thresholds and output voltage levels ensure interoperability without level-shifting.
What is the function of the NC pins on the DS1013S-10 16-pin SOIC package?
The DS1013S-10 has nine NC (No Connection) pins-pins 2, 3, 6, 8, 9, 10, 15, and 16-plus pin 5 designated as IN3 (not NC). These NC pins are internally unconnected and must remain unconnected on the PCB; they serve mechanical compatibility with other DS1013 variants and do not require termination or grounding.
Is the DS1013S-10 RoHS compliant and lead-free?
Yes, the DS1013S-10 is RoHS compliant and lead-free. Dallas Semiconductor's product change notices and Maxim Integrated's packaging documentation confirm that all DS1013S variants manufactured post-2006 meet RoHS Directive 2011/65/EU requirements, including exemption 7a for lead in high-melting-temperature solder alloys.
DS1013S-10 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 10ns
- Tap Increment:
- -
- Available Total Delays:
- 10ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DS1013S-10 FAQ
1.How can I place an order for DS1013S-10 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1013S-10 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1013S-10 reliable?
The price and inventory of DS1013S-10 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1013S-10 is usually 5 days.
3.What payment methods are accepted for DS1013S-10?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1013S-10 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1013S-10?
DS1013S-10 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1013S-10 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1013S-10?
For technical support, including DS1013S-10 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1013S-10 requirements.
6.How does Aetrix verify that DS1013S-10 is sourced from the original manufacturer or authorized distributors?
All DS1013S-10 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1013S-10 meets industry standards.
7.What is the process for return or replacement of DS1013S-10?
All DS1013S-10 units undergo pre-shipment inspection (PSI). If there is an issue with DS1013S-10, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1013S-10 part is unused and in its original packaging.
Return procedure for DS1013S-10:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1013S-10 Tags

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