Analog Devices Inc./Maxim Integrated DS1035M-8
- Part No.:
- DS1035M-8
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
DS1035M-8.pdf
- Description:
- 3-IN-1 HIGH-SPEED DELAY LINE
- Quantity:
- Payment:

- Shipping:

Inventory:2,541
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Product details
Overview
DS1035M-8 from Maxim Integrated (formerly Dallas Semiconductor) is a high-speed, all-silicon 3-in-1 delay line operating at +5 V with three independent buffered outputs, 8 ns nominal delay per channel, ±2.0 ns initial tolerance, and ±1.5 ns additional tolerance over temperature/voltage. It delivers precise leading/trailing edge timing for clock skew management in digital test equipment and FPGA synchronization.
For engineers reviewing the DS1035M-8 datasheet, DS1035M-8 pinout, DS1035M-8 application, or DS1035M-8 equivalent, this page provides verified timing accuracy, DIP-8 package details, load-driving capability (10 LS loads), and validated alternatives for high-speed logic delay substitution.
Technical Context
The DS1035M-8 implements three identical, fully buffered delay paths with matched tPLH/tPHL propagation characteristics. Each output maintains input signal symmetry via edge-preserving design, supporting stable operation across 0°C to +85°C and 4.75 V to 5.25 V supply range.
It uses monolithic silicon delay architecture-no external components required-and features low output rise/fall times (2.0–2.5 ns), 100 ms power-up time, and compatibility with standard 50 Ω source impedance and 15 pF capacitive load test conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Nominal Delay | 8 ns per output (tPLH/tPHL); enables precise 8 ns clock/data alignment in high-speed digital systems |
| Initial Tolerance | ±2.0 ns; sets worst-case timing margin at room temperature before thermal/voltage drift |
| Tolerance Over Temp/Vcc | ±1.5 ns (0°C to +85°C, 4.75–5.25 V); defines total delay variation envelope in industrial environments |
| Output Drive Strength | 12 mA sink / –1.0 mA source; supports direct interfacing to 10 LS-TTL loads without buffering |
| Supply Voltage | +5.0 V ±5% (4.75–5.25 V); compatible with legacy 5 V logic rails and mixed-voltage board designs |
| Operating Temperature | –40°C to +85°C; qualified for extended industrial applications beyond commercial-grade limits |
| Rise/Fall Time | 2.0–2.5 ns; ensures minimal pulse distortion and preserves signal integrity at >100 MHz edge rates |
Pinout & Package
DS1035M-8 is housed in an 8-pin plastic dual in-line package (PDIP), 300 mil width, with standard through-hole mounting and vapor-phase/IR/wave solder compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | IN1 | First independent input signal path; accepts TTL/CMOS-compatible logic levels |
| 2 | IN2 | Second independent input signal path; electrically isolated from IN1 and IN3 |
| 3 | IN3 | Third independent input signal path; enables parallel multi-channel delay distribution |
| 4 | GND | Digital ground reference; must be connected to system ground plane for noise immunity |
| 5 | VCC | +5 V power supply; requires local 0.1 µF ceramic decoupling capacitor near pin |
| 6 | OUT3 | Delayed output corresponding to IN3; matches IN3 timing with 8 ns offset |
| 7 | OUT1 | Delayed output corresponding to IN1; matches IN1 timing with 8 ns offset |
| 8 | OUT2 | Delayed output corresponding to IN2; matches IN2 timing with 8 ns offset |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon delay architecture | Eliminates aging, drift, and reliability issues associated with analog RC or SAW-based delay solutions |
| Precision edge preservation | Maintains input duty cycle and symmetry across both rising and falling edges within ±1.5 ns tolerance |
| Three independent buffered delays | Enables simultaneous delay of three separate signals without crosstalk or loading interaction |
| Standard DIP-8 footprint | Supports drop-in replacement in legacy test fixtures and prototyping boards using through-hole assembly |
| 10 LS-TTL load drive capability | Reduces need for external fanout buffers in logic-level timing circuits |
Applications
| Logic Analyzer Timing Calibration | FPGA Clock Skew Compensation |
|---|---|
|
Use Scenario: Calibrating internal trigger timing offsets between multiple acquisition channels in benchtop logic analyzers. IC Role / Device Role / Timing Role: DS1035M-8 provides deterministic, repeatable 8 ns delay on reference clock paths to align sampling windows across channels. Use Value: Enables sub-nanosecond inter-channel timing correlation without custom PCB trace tuning or external delay lines. |
Use Scenario: Compensating for routing-induced clock skew between FPGA I/O banks driving synchronous memory interfaces. IC Role / Device Role / Timing Role: DS1035M-8 inserts matched delay on clock or strobe lines to realign setup/hold timing margins across parallel data lanes. Use Value: Achieves reliable DDR2/DDR3 interface timing closure without modifying FPGA pin assignments or layout. |
| Digital Test Equipment Signal Alignment | High-Speed Serial Link Jitter Testing |
|
Use Scenario: Aligning stimulus and response paths in automated test equipment (ATE) for timing margin verification. IC Role / Device Role / Timing Role: DS1035M-8 applies identical 8 ns delay to both DUT input and reference capture paths to eliminate fixed-path skew. Use Value: Improves measurement repeatability by removing systematic timing bias from test fixture asymmetry. |
Use Scenario: Injecting controlled, repeatable jitter into serial data streams during receiver stress testing (e.g., PCIe, SATA). IC Role / Device Role / Timing Role: DS1035M-8 modulates edge position of a clean clock source feeding a pattern generator to create calibrated jitter waveforms. Use Value: Generates known-amplitude jitter (±8 ns peak-to-peak) traceable to device specification, not arbitrary oscillator drift. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-channel logic delay applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1035Z-8 | Same 8 ns delay, ±2.0 ns initial tolerance, but SOIC-8 (150-mil) package; operates 0°C to +70°C only | Limited to surface-mount assembly and commercial-temperature applications; no extended temp support | Select DS1035Z-8 only if board space constraints require SOIC and ambient temperature stays below +70°C |
| MAX9601EPA+ | Single-output, 10 ns delay, ±1.0 ns initial tolerance, 3.3 V operation; different voltage domain and channel count | Not a functional substitute for 3-channel operation; requires three devices plus level-shifting for 5 V systems | Choose MAX9601EPA+ only when migrating to 3.3 V logic and single-delay-per-package architecture is acceptable |
Compared with DS1035M-8, DS1035Z-8 offers identical timing performance in a smaller footprint but sacrifices industrial temperature range and through-hole compatibility; MAX9601EPA+ provides tighter initial tolerance but demands redesign for voltage translation and channel replication.
Availability
DS1035M-8 is available at Aetrix Electronics and suitable for digital test equipment, FPGA-based embedded controllers, and high-speed serial interface validation requiring stable component supply with guaranteed long-term availability.
Supply support for DS1035M-8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (acquired Dallas Semiconductor in 2001) is a U.S.-based semiconductor company specializing in analog, mixed-signal, and high-reliability timing solutions for industrial, communications, and test equipment markets.
The DS1035 series was designed specifically for high-speed digital systems needing deterministic, multi-channel logic delays with guaranteed edge fidelity-targeting logic analyzer calibration, ATE signal alignment, and FPGA timing compensation.
FAQ
What is the operating temperature range for DS1035M-8?
The DS1035M-8 is rated for operation from –40°C to +85°C, making it suitable for extended industrial environments where commercial-grade parts (0°C to +70°C) would fail. This range is confirmed in the package-specific ordering information table and supported by its qualification under industrial thermal cycling profiles.
Does DS1035M-8 support 3.3 V logic inputs?
No, DS1035M-8 is a +5 V device with VIH minimum of 2.2 V and VIL maximum of 0.8 V-designed for TTL/LS-TTL compatibility. It does not support direct 3.3 V logic interfacing without level translation, as its input thresholds and supply rail are fixed to 5 V operation.
Can DS1035M-8 drive standard CMOS loads?
Yes, DS1035M-8 can drive standard CMOS loads, but its output drive strength (12 mA sink, –1.0 mA source) is optimized for LS-TTL (10 loads). For high-capacitance CMOS buses, verify load capacitance ≤15 pF and consider adding series termination to maintain edge integrity.
Is DS1035M-8 RoHS compliant?
No, DS1035M-8 is not RoHS/lead-free compliant, as explicitly stated in the ordering information table: "RoHS/Lead-Free: No". It contains leaded solder finish and should be used only in exempt or non-RoHS-restricted applications.
How is delay accuracy specified for DS1035M-8?
DS1035M-8 delay accuracy is specified as ±2.0 ns initial tolerance at +25°C, plus ±1.5 ns additional variation over full temperature (–40°C to +85°C) and supply (4.75–5.25 V) ranges-applying to both tPLH and tPHL on all three outputs simultaneously.
DS1035M-8 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Bulk
- Product Status:
- Active
- Number of Taps/Steps:
- -
- Function:
- Multiple, NonProgrammable
- Delay to 1st Tap:
- 8ns
- Tap Increment:
- -
- Available Total Delays:
- 8ns
- Number of Independent Delays:
- 3
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
DS1035M-8 FAQ
1.How can I place an order for DS1035M-8 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1035M-8 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1035M-8 reliable?
The price and inventory of DS1035M-8 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1035M-8 is usually 5 days.
3.What payment methods are accepted for DS1035M-8?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1035M-8 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1035M-8?
DS1035M-8 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1035M-8 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1035M-8?
For technical support, including DS1035M-8 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1035M-8 requirements.
6.How does Aetrix verify that DS1035M-8 is sourced from the original manufacturer or authorized distributors?
All DS1035M-8 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1035M-8 meets industry standards.
7.What is the process for return or replacement of DS1035M-8?
All DS1035M-8 units undergo pre-shipment inspection (PSI). If there is an issue with DS1035M-8, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1035M-8 part is unused and in its original packaging.
Return procedure for DS1035M-8:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1035M-8 Tags

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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