Analog Devices Inc./Maxim Integrated DS1035Z-6/T&R

Overview

DS1035Z-6/T&R from Dallas Semiconductor (now Maxim Integrated) is a 3-channel, all-silicon, high-speed delay line IC operating at +5 V with three independent buffered outputs. It delivers precise 6 ns nominal delay per channel (tPLH/tPHL), ±1.5 ns initial tolerance, and ±1.0 ns additional variation over 0°C to 70°C and 4.75–5.25 V. Used in clock skew management and signal alignment for high-speed digital systems.

For engineers reviewing the DS1035Z-6/T&R datasheet, DS1035Z-6/T&R pinout, DS1035Z-6/T&R application, or DS1035Z-6/T&R equivalent, key selection criteria include guaranteed edge-aligned delay accuracy, LS-TTL load drive capability (10 loads per output), SOIC-8 (150-mil) packaging, and compatibility with vapor-phase, IR, and wave soldering processes.

Technical Context

The DS1035Z-6/T&R implements three identical, fully buffered delay paths with matched tPLH and tPHL propagation characteristics. Each path preserves input pulse symmetry via leading- and trailing-edge precision timing referenced to the 1.5 V logic threshold under 15 pF load.

It operates within strict DC electrical limits: supply current ≤35 mA at 5.25 V/1 µs period, VIH ≥2.2 V, VIL ≤0.8 V, and output drive of –1.0 mA (IOH) / +12 mA (IOL) at specified VOH/VOL conditions. Power-up time is 100 ms.

Key Specifications

Pinout & Package

DS1035Z-6/T&R is housed in an 8-pin SOIC package (150-mil width), RoHS-compliant and tape-and-reel packaged for automated assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-channel fixed-delay line applications.

Compared with DS1035M-6 and DS1035-60, the DS1035Z-6/T&R uniquely combines SOIC-8 surface-mount compatibility, tape-and-reel packaging for pick-and-place, and guaranteed 6 ns delay with ±1.5 ns initial tolerance-making it optimal for volume SMT production of timing-critical digital systems.

Availability

DS1035Z-6/T&R is available at Aetrix Electronics and suitable for high-speed clock distribution, logic signal skew compensation, and test equipment signal conditioning requiring stable component supply and full traceability.

Supply support for DS1035Z-6/T&R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Dallas Semiconductor, now part of Maxim Integrated (acquired 2001), specialized in precision analog, timing, and mixed-signal ICs for industrial and communications infrastructure.

The DS1035 series was designed specifically as a high-speed, all-silicon replacement for legacy analog delay solutions-targeting applications demanding repeatable, temperature-stable, edge-aligned delays in +5 V digital systems.

FAQ

What is the exact delay value and tolerance specification for DS1035Z-6/T&R?

The DS1035Z-6/T&R provides a nominal delay of 6 ns per output (tPLH and tPHL), with an initial tolerance of ±1.5 ns at +25°C and VCC = +5.0 V. Over the full operating range (0°C to 70°C, 4.75–5.25 V), total delay variation remains within ±1.0 ns beyond initial tolerance, as confirmed in Table 1 of the official DS1035 datasheet.

Is DS1035Z-6/T&R pin-compatible with other DS1035 variants like DS1035M-6 or DS1035-60?

Yes - DS1035Z-6/T&R shares identical pinout and electrical behavior with DS1035M-6 (DIP-8) and DS1035-60 (SOIC-8). All three use the same internal die and timing architecture. The only differences are package type (SOIC vs. DIP) and marking convention; DS1035Z-6/T&R and DS1035-60 are both SOIC-8 and functionally identical in circuit design.

Can DS1035Z-6/T&R drive standard TTL or CMOS loads directly?

Yes - DS1035Z-6/T&R is rated to drive up to 10 LS-TTL loads per output, with IOL = +12 mA and IOH = –1.0 mA at specified VOH/VOL conditions. It meets standard TTL voltage thresholds (VIH ≥ 2.2 V, VIL ≤ 0.8 V) and interfaces directly with 74LS, 74F, and most 5 V CMOS families without level-shifting or buffering.

What is the maximum operating frequency or minimum pulse width supported by DS1035Z-6/T&R?

DS1035Z-6/T&R supports input pulse widths equal to or greater than 100% of its tap delay (i.e., ≥6 ns), per AC Electrical Characteristics. Its usable frequency limit is governed by input pulse width and period constraints - with tPERIOD ≥ 2 × tWI. For 6 ns delay, minimum practical period is ~12 ns (~83 MHz fundamental), though reliable operation depends on clean edge rates (<3 ns) and proper 15 pF load termination.

Does DS1035Z-6/T&R require external decoupling capacitors, and if so, what value is recommended?

Yes - DS1035Z-6/T&R requires a 0.1 µF ceramic decoupling capacitor placed as close as possible between VCC and GND pins. This is explicitly required to maintain stable internal biasing and minimize supply-induced jitter, especially given its sensitivity to edge-aligned timing accuracy and 35 mA active current draw at 1 µs period.