Analog Devices Inc./Maxim Integrated DS1040Z-B40
- Part No.:
- DS1040Z-B40
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Delay Lines
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS1040Z-B40.pdf
- Description:
- IC DELAY LINE 5TAP 40NS 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,403
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Product details
Overview
DS1040Z-B40 from Dallas Semiconductor (now Maxim Integrated) is a rising-edge-triggered, CMOS programmable one-shot pulse generator with five precise output widths (20 ns to 40 ns), ±5% or ±2 ns width tolerance, and dual inverting/non-inverting outputs. It operates at 5 V, drives up to five 74LS loads, and is used in laser power control for magneto-optical disk read/write systems.
For engineers reviewing the DS1040Z-B40 datasheet, DS1040Z-B40 pinout, DS1040Z-B40 application, or DS1040Z-B40 equivalent, key selection criteria include programmable pulse width resolution (5 ns steps), intrinsic delay ≤10 ns, TTL/CMOS compatibility, SOIC-8 packaging, and temperature-stable timing across 0°C to 70°C.
Technical Context
The DS1040Z-B40 implements a parallel-programmed, edge-triggered monostable multivibrator using all-silicon CMOS logic. Its pulse width is determined by the logic states of three binary programming pins (P2, P1, P0), selecting one of five fixed widths per variant - for DS1040Z-B40, those are 20 ns, 25 ns, 30 ns, 35 ns, and 40 ns.
It features dual complementary outputs (OUT and OUT̅), intrinsic delay ≤10 ns measured between 1.5 V points, and guaranteed operation under 5.0 V ±5% supply. Input trigger requires ≥5 ns high/low pulse width and meets TTL/CMOS voltage thresholds (VIH ≥2.2 V, VIL ≤0.8 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Pulse Widths | 20 ns, 25 ns, 30 ns, 35 ns, 40 ns - selectable via P2/P1/P0; no external components required |
| Width Accuracy | ±5% or ±2 ns, whichever is greater - ensures predictable timing in closed-loop laser control |
| Intrinsic Delay (tD) | 0–10 ns - enables tight synchronization between trigger and output edges |
| Supply Voltage | 4.75 V to 5.25 V - compatible with standard 5 V TTL/CMOS logic rails |
| Output Drive | Drives ≥5 LS-TTL loads - sufficient for direct interface to standard logic families without buffering |
| Operating Temperature | 0°C to +70°C - validated for commercial-grade embedded systems and optical storage equipment |
| Input Trigger Edge | Rising-edge sensitive - eliminates ambiguity in multi-source trigger environments |
Pinout & Package
DS1040Z-B40 is housed in an 8-pin SOIC package (150-mil width), surface-mount compatible and vapor-phase/wave solderable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN | Trigger input | Rising-edge-sensitive digital input; requires ≥5 ns pulse width and TTL/CMOS-compatible voltage levels |
| P2, P1, P0 | Width programming inputs | 3-bit parallel select lines; determine output width per Table 1 (e.g., 100 = 40 ns for DS1040Z-B40) |
| GND | Ground reference | Return path for supply and signal; must be low-impedance for stable timing |
| OUT | Non-inverted pulse output | Active-high pulse matching programmed width; drives 74LS loads directly |
| OUT̅ | Inverted pulse output | Complementary to OUT; supports differential signaling or dual-gate control |
| VCC | Positive supply | +5 V ±5%; decoupling capacitor recommended near pin for noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| All-silicon CMOS construction | Eliminates hybrid packaging drift and improves long-term reliability in optical drive environments |
| Programmable width selection | Five discrete, factory-trimmed widths (20–40 ns) selected via static logic pins - no trimming resistors or EEPROM needed |
| Dual complementary outputs | Simultaneous OUT and OUT̅ enable single-chip control of push-pull laser drivers or redundant timing paths |
| Low intrinsic delay | ≤10 ns delay from IN to OUT ensures sub-10 ns jitter contribution in time-critical laser gating |
| Wave/vapor-phase solderable | SOIC-8 footprint supports automated PCB assembly without reflow damage or lead fatigue |
Applications
| Laser Power Gating | Magneto-Optical Disk Write Control |
|---|---|
Use Scenario: Precise on/off control of semiconductor laser diode current during write cycles in MO disk drives. IC Role / Device Role / Timing Role: One-shot pulse generator providing gate-enable pulses synchronized to head positioning signals. Use Value: 40 ns maximum width and ±2 ns absolute tolerance ensure consistent laser exposure duration, minimizing bit-error rate. | Use Scenario: Generating timed enable pulses for magnetic field modulation during data writing on magneto-optical media. IC Role / Device Role / Timing Role: Programmable width generator delivering accurate, repeatable pulse durations to driver ICs controlling coil current. Use Value: Five discrete widths (20–40 ns) allow fine-tuning of magnetic field rise/fall profiles without firmware changes. |
| Optical Pickup Timing Calibration | Digital Logic Test Stimulus |
Use Scenario: Calibrating timing margins between focus/track actuator response and laser emission in optical pickup assemblies. IC Role / Device Role / Timing Role: Reference pulse source with known, stable width for measuring system propagation delays. Use Value: Intrinsic delay ≤10 ns and width tolerance ±2 ns provide traceable timing baseline for production test fixtures. | Use Scenario: Injecting controlled-width pulses into digital logic circuits to verify setup/hold timing or glitch immunity. IC Role / Device Role / Timing Role: Deterministic pulse source generating repeatable, sub-50 ns stimuli for functional validation. Use Value: Dual outputs support simultaneous stimulus and observation; 5 ns step resolution enables margin testing at process corners. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable pulse generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1040M-B40 | Same electrical specs and programming logic, but in 8-pin DIP (300-mil) package | Used where through-hole assembly or prototyping breadboarding is required | Select DS1040M-B40 for manual assembly or legacy PCBs; DS1040Z-B40 for space-constrained SMT designs |
| MAX1040Z-B40 | Pin- and function-compatible successor; identical timing specs, improved ESD rating (±4 kV HBM) | Preferred for new designs requiring enhanced robustness in manufacturing or field environments | Choose MAX1040Z-B40 when higher ESD immunity or longer product lifecycle is critical |
Compared with DS1040M-B40 and MAX1040Z-B40, the DS1040Z-B40 offers identical pulse width accuracy and delay performance in a compact SOIC-8 package, making it optimal for high-density optical storage PCBs where board area and automated assembly are prioritized.
Availability
DS1040Z-B40 is available at Aetrix Electronics and suitable for magneto-optical disk drives, laser diode control modules, optical pickup calibration systems, and digital test stimulus generators requiring stable component supply and verified timing performance.
Supply support for DS1040Z-B40 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Dallas Semiconductor, now part of Maxim Integrated (a subsidiary of Analog Devices), specialized in precision timing, memory, and mixed-signal ICs for industrial, computing, and optical storage applications.
The DS1040 series was designed specifically for high-reliability, programmable pulse generation in magneto-optical and laser-based systems - emphasizing width stability, low delay, and direct TTL/CMOS interfacing without external components.
FAQ
What is the exact pulse width range supported by DS1040Z-B40?
The DS1040Z-B40 provides five discrete, factory-programmed pulse widths: 20 ns, 25 ns, 30 ns, 35 ns, and 40 ns. These values are selected via the P2/P1/P0 programming pins and are guaranteed within ±5% or ±2 ns, whichever is greater, over 0°C to +70°C. The DS1040Z-B40 does not support widths outside this set - unlike broader variants such as DS1040-500.
Does DS1040Z-B40 require external components for operation?
No, the DS1040Z-B40 operates autonomously with only a 5 V supply, ground, trigger input, and programming pins. No external capacitors, resistors, or trimmers are needed - all timing is implemented in silicon. A 0.1 µF ceramic decoupling capacitor on VCC is recommended for noise suppression, but it is not part of the core timing circuitry of the DS1040Z-B40.
What is the maximum load DS1040Z-B40 can drive directly?
The DS1040Z-B40 is specified to drive up to five 74LS TTL loads per output (OUT or OUT̅). This corresponds to a low-level output current (IOL) of 8 mA and high-level output current (IOH) of –1 mA at VCC = 4.75 V. Exceeding this load may degrade pulse width accuracy or increase intrinsic delay beyond the 10 ns max spec for the DS1040Z-B40.
Is DS1040Z-B40 compatible with 3.3 V logic systems?
No - the DS1040Z-B40 is strictly a 5 V device. Its absolute maximum VCC is +7.0 V, minimum operating VCC is 4.75 V, and input thresholds (VIH ≥2.2 V, VIL ≤0.8 V) assume a 5 V rail. Interfacing with 3.3 V systems requires level translation; the DS1040Z-B40 itself does not support 3.3 V operation or mixed-voltage I/O.
How is pulse width selected on DS1040Z-B40?
Pulse width on the DS1040Z-B40 is selected by applying static logic levels (VCC or GND) to the three programming pins P2, P1, and P0. For DS1040Z-B40, the code "100" (P2=1, P1=0, P0=0) selects the maximum width of 40 ns; other combinations yield 20 ns, 25 ns, 30 ns, or 35 ns per Table 1 in the DS1040Z-B40 datasheet.
DS1040Z-B40 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Number of Taps/Steps:
- 5
- Function:
- 1-Shot, Programmable
- Delay to 1st Tap:
- 20ns
- Tap Increment:
- 5 ns
- Available Total Delays:
- 40ns
- Number of Independent Delays:
- 1
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS1040Z-B40 FAQ
1.How can I place an order for DS1040Z-B40 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1040Z-B40 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1040Z-B40 reliable?
The price and inventory of DS1040Z-B40 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1040Z-B40 is usually 5 days.
3.What payment methods are accepted for DS1040Z-B40?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1040Z-B40 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1040Z-B40?
DS1040Z-B40 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1040Z-B40 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1040Z-B40?
For technical support, including DS1040Z-B40 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1040Z-B40 requirements.
6.How does Aetrix verify that DS1040Z-B40 is sourced from the original manufacturer or authorized distributors?
All DS1040Z-B40 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1040Z-B40 meets industry standards.
7.What is the process for return or replacement of DS1040Z-B40?
All DS1040Z-B40 units undergo pre-shipment inspection (PSI). If there is an issue with DS1040Z-B40, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1040Z-B40 part is unused and in its original packaging.
Return procedure for DS1040Z-B40:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS1040Z-B40 Tags

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LTC6994CS6-1#TRMPBF
Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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Analog Devices Inc.

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LTC6994HS6-2#TRMPBF
Analog Devices Inc.

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Analog Devices Inc.

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DS1124U-25+T
Analog Devices Inc./Maxim Integrated
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