Analog Devices Inc./Maxim Integrated DS1073Z-60

Overview

DS1073Z-60 from Maxim Integrated is a user-programmable 3V fixed-frequency oscillator with dual outputs, delivering up to 60.000 MHz from internal oscillator or external reference, ±0.5% initial accuracy, 2.7–3.6 V supply, and synchronous output enable. It serves as a programmable clock source in embedded timing control, FPGA configuration, and microcontroller clocking applications.

For engineers reviewing the DS1073Z-60 datasheet, DS1073Z-60 pinout, DS1073Z-60 application, or DS1073Z-60 equivalent, key selection considerations include its non-volatile register programming capability, glitch-free OE/SELX switching, power-down current of 0.8 µA, and support for crystal, external clock, or internal oscillator reference modes.

Technical Context

The DS1073Z-60 implements a master oscillator followed by a user-selectable prescaler (÷1, ÷2, ÷4) and a 9-bit programmable divider (N = 2 to 513), enabling precise frequency synthesis across 29.3 kHz–60 MHz. Its architecture supports on-the-fly reference switching between internal oscillator and external/crystal sources via the PDN/SELX pin when configured in SEL mode.

It features two synchronized outputs: I/O (main programmable output) and OUT0 (reference output, unaffected by OE but disabled during power-down), both with 40–60% duty cycle and ≤100 ps jitter (3σ). The device uses EEPROM-stored register settings (MUX and DIV words) for persistent configuration across power cycles.

Key Specifications

Pinout & Package

DS1073Z-60 is housed in a 150-mil SOIC-8 package (JEDEC MS-012AC), with lead finish SnPb and RoHS-compliant variants available per ordering suffix.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Compared with Si51212-D-GM and ICS843002AGI-01LFT, the DS1073Z-60 provides unique value in cost-sensitive, space-constrained designs requiring field-programmable division, crystal compatibility, and ultra-low power-down current-without demanding complex serial configuration or high-speed signaling.

Availability

DS1073Z-60 is available at Aetrix Electronics and suitable for microcontroller clocking, FPGA configuration, industrial PLC timing, and legacy system upgrades requiring stable component supply and long-term obsolescence management.

Supply support for DS1073Z-60 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Maxim Integrated (now part of Analog Devices) designs precision analog, mixed-signal, and timing ICs for industrial, computing, and communications markets.

The DS1073 product line delivers programmable, self-contained clock generators targeting cost-optimized embedded systems needing flexible, zero-component timing solutions with EEPROM-based configurability.

FAQ

What is the factory default output frequency of the DS1073Z-60?

The DS1073Z-60 ships from the factory configured for half its maximum operating frequency: 30.000 MHz. This default is set via EEPROM-stored MUX and DIV register values (DIV = 0x000, MSEL = 1, E/I = 0), and can be reprogrammed in-system using the 1-Wire interface before board assembly. The DS1073Z-60 retains this setting across power cycles due to non-volatile memory storage.

Can the DS1073Z-60 operate with a crystal, and what are the constraints?

Yes, the DS1073Z-60 supports fundamental-mode crystals connected between OSCIN and XTAL pins, with a maximum rated frequency of 25 MHz. The crystal must be operated in fundamental mode only-not overtone-and no external load capacitors are required. If a crystal is not used, the XTAL pin must be left unconnected (open). The DS1073Z-60 automatically routes the crystal signal through its internal oscillator circuitry when E/I = 1 or PDN = 0 and SELX is low.

How does the DS1073Z-60 achieve glitch-free output enable (OE) behavior?

The DS1073Z-60 uses an internal "enabling sequencer" that samples OE synchronously to the prescaler output (MCLK) and gates the final output based on the programmable divider state. When OE goes low, the I/O pin is held low at the next high-to-low transition-never mid-pulse-ensuring no truncated output pulses. This guarantees deterministic phase alignment upon re-enable, critical for synchronous digital systems. The DS1073Z-60 implements this behavior without external logic or delay elements.

What is the power-up sequence timing for the DS1073Z-60, and how does it affect system initialization?

The DS1073Z-60 requires approximately 256 cycles of the master clock (MCLK) to stabilize after power-on or exit from power-down mode, resulting in a typical tSTAB of 0.1–1 ms. During this interval, outputs remain inactive until stabilization completes. To avoid delays, OE should be asserted high before or during power-up; holding OE low postpones tSTAB initiation. The DS1073Z-60's power-on reset sequence ensures reliable register loading and oscillator lock before enabling I/O or OUT0.

Is the DS1073Z-60 pin-compatible with other DS1073 variants such as DS1073Z-80 or DS1073Z-100?

Yes, all DS1073Z-x variants-including DS1073Z-60, DS1073Z-80, and DS1073Z-100-share identical 150-mil SOIC-8 pinouts, electrical characteristics, and register architecture. They differ only in factory-programmed maximum frequency capability and corresponding internal oscillator trim. This allows direct substitution in existing layouts when frequency headroom or thermal margin adjustments are needed, provided the target application does not exceed the variant's specified max output frequency.