Analog Devices Inc./Maxim Integrated DS1075M-100
- Part No.:
- DS1075M-100
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Category:
- Programmable Timers and Oscillators
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
DS1075M-100.pdf
- Description:
- IC OSC DUAL FX FREQ 100MHZ 8-DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS1075M-100 from Maxim Integrated is a user-programmable fixed-frequency oscillator IC with dual outputs, delivering up to 100.000 MHz output frequency, ±0.5% initial tolerance, and 1% combined variation over temperature and supply voltage. It integrates on-chip prescaler (÷1/2/4), programmable divider (N = 2–513), nonvolatile EEPROM register storage, and supports internal oscillator, external clock, or crystal reference inputs - used in embedded timing control, FPGA clocking, and programmable logic systems.
For engineers reviewing the DS1075M-100 datasheet, DS1075M-100 pinout, DS1075M-100 application, or DS1075M-100 equivalent, this page provides verified functional identity, confirmed pin roles, validated package mapping (300-mil DIP), real-world timing behavior (synchronous OE gating, glitch-free SELX switching), and two field-validated alternative parts for frequency-flexible clock generation.
Technical Context
The DS1075M-100 implements a master oscillator followed by a user-selectable prescaler and a 9-bit programmable divider (N = 2–513), enabling precise output frequencies from 29.3 kHz to 100 MHz. Its architecture supports three reference sources - internal oscillator, external clock (≤50 MHz), or crystal (≤25 MHz) - selected via EEPROM-configurable E/I bit or dynamic SELX pin control when PDN=0.
It features synchronous output enable (OE) with glitchless gating, power-down mode (PDN) that disables oscillator and buffers to 0.8 µA, and dual-output capability: main output (IN/OUT) and reference output (OUT0), where OUT0 remains active during OE assertion but is disabled during power-down. All register settings (MUX/DIV words) are stored nonvolatily in on-chip EEPROM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Output Frequency | 100.000 MHz - defines upper limit of programmable clock output for high-speed digital logic and FPGA interfaces. |
| Initial Frequency Tolerance | ±0.5% at 25°C - ensures accurate timing without factory trimming or external calibration. |
| Temp/Voltage Variation | ±1% - guarantees stable operation across 0°C to 70°C and VCC = 4.75–5.25 V without derating. |
| Programmable Divider Range | N = 2 to 513 - enables fine-grained frequency synthesis (e.g., 100 MHz ÷ 513 ≈ 195 kHz) with integer-only division. |
| Prescaler Options | ÷1 (bypass), ÷2, ÷4 - allows coarse scaling before N-divider, supporting wide frequency coverage with minimal register changes. |
| Supply Current (Active) | 35 mA - measured at CL = 15 pF, both outputs enabled; confirms suitability for low-to-moderate power clock distribution. |
| Power-Down Current | 0.8 µA - enables ultra-low-power sleep states in battery-backed or energy-sensitive systems. |
Pinout & Package
DS1075M-100 is housed in an industry-standard 300-mil 8-pin DIP package (suffix "M"), compatible with through-hole PCB assembly and socket-based prototyping. Pin spacing and footprint match JEDEC MS-001BA.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: IN/OUT | Programmable I/O | Serial programming input during power-up with pull-up; becomes main oscillator output (OUT) in operation mode. |
| 2: OUT0 | Reference Output | Buffered master clock (MCLK) output; unaffected by OE, disabled only in power-down; configurable via EN0 bit. |
| 3: VCC | Power Supply | +5 V ±5% supply input; powers all internal circuitry including oscillator, dividers, and output drivers. |
| 4: GND | Ground Reference | Primary return path for VCC and all signal currents; must be low-impedance for jitter-sensitive timing. |
| 5: OSCIN | External Clock Input | Accepts ≤50 MHz CMOS-level clock signal; used when external reference is selected (E/I = 1 or SELX = 0). |
| 6: PDN/SELX | Mode Control | Configurable as active-low power-down (PDN=1) or dynamic reference selector (PDN=0); function set in MUX register. |
| 7: XTAL | Crystal Terminal | Connects to one side of crystal (other side to OSCIN); left open if crystal not used; enables ≤25 MHz crystal reference. |
| 8: OE | Output Enable | Active-high synchronous gate: holds OUT low at next H→L transition (no pulse truncation); preserves phase alignment. |
Key Features
| Feature | Design Value |
|---|---|
| No external components required | Self-contained oscillator core eliminates load capacitors, feedback resistors, or trimmers - reduces BOM count and layout area. |
| User-programmable EEPROM registers | Nonvolatile MUX/DIV words retain configuration across power cycles; enables field reprogramming without hardware change. |
| Synchronous output enable (OE) | Guarantees no truncated pulses: OUT transitions only at defined edges, preserving duty cycle integrity in timing-critical systems. |
| Glitch-free reference switching (SELX) | Enables dynamic switch between internal/external clocks with deterministic latency (tSIE ≤ 3tI/2 + tE), avoiding metastability. |
| Dual independent outputs | IN/OUT delivers final divided clock; OUT0 provides unmodified MCLK - supports clock domain bridging and debug monitoring. |
Applications
| FPGA Clock Distribution | Industrial PLC Timing |
|---|---|
Use Scenario: Providing configurable, stable clock signals to multiple FPGA banks with varying speed grade requirements. IC Role / Device Role / Timing Role: Primary clock source generating synchronized, divided clocks (e.g., 100 MHz → 50 MHz, 25 MHz) via on-chip prescaler/divider. Use Value: Eliminates need for multiple discrete oscillators or external PLLs; single DS1075M-100 replaces up to four fixed-frequency crystals. |
Use Scenario: Delivering robust, temperature-stable timing to microcontroller-based motion control loops in factory automation equipment. IC Role / Device Role / Timing Role: System clock generator with ±1% stability over 0°C–70°C and 4.75–5.25 V supply range. Use Value: Maintains deterministic instruction timing under voltage sags and ambient thermal drift - critical for servo loop consistency. |
| Communications Baseband Timing | Test Equipment Signal Generation |
Use Scenario: Generating precise sampling clocks for ADC/DAC interfaces in wireless baseband processors. IC Role / Device Role / Timing Role: Low-jitter (100 ps typ.) clock source feeding data converters; configured via EEPROM for production variants. Use Value: Reduces SNR degradation from clock-induced aperture uncertainty; supports multi-rate sampling via N-divider reprogramming. |
Use Scenario: Serving as a flexible, reprogrammable clock engine in benchtop signal generators and logic analyzers. IC Role / Device Role / Timing Role: Programmable reference oscillator enabling user-defined output frequencies from 29.3 kHz to 100 MHz. Use Value: Enables single-hardware platform to emulate diverse clock standards (e.g., PCIe, USB, Ethernet) without component swaps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable oscillator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS1077Z-100 | SOIC-8 package (150-mil), identical electrical specs and register map; same 100 MHz max output and EEPROM programming interface. | Requires surface-mount assembly; lacks through-hole compatibility; better suited for space-constrained PCBs. | Select DS1077Z-100 when board real estate is limited and reflow soldering is available; otherwise DS1075M-100 preferred for prototyping and repairability. |
| Si5351A-B-GM | 3-output I²C-programmable clock generator (0.1–200 MHz), higher integration, but requires external crystal and I²C host controller. | Supports multi-frequency simultaneous outputs and fractional synthesis; not pin-compatible and demands firmware integration. | Choose Si5351A-B-GM for systems needing >2 clocks or sub-Hz resolution; DS1075M-100 remains optimal for single-output, standalone, low-complexity timing. |
Compared with DS1075M-100, DS1077Z-100 offers identical functionality in SOIC packaging for automated assembly, while Si5351A-B-GM adds multi-output flexibility and finer frequency resolution at the cost of system-level complexity and external dependencies.
Availability
DS1075M-100 is available at Aetrix Electronics and suitable for FPGA clocking, industrial PLC timing, and communications baseband applications requiring stable component supply, long-term lifecycle support, and through-hole manufacturability.
Supply support for DS1075M-100 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Maxim Integrated (now part of Analog Devices) designs precision analog and mixed-signal ICs for industrial, communications, and computing markets, emphasizing reliability, integration, and ease of use.
The DS1075M-100 belongs to Maxim's EconOscillator™ family - engineered for cost-sensitive, programmable clock generation in embedded systems where flexibility, low component count, and field configurability are essential.
FAQ
What is the maximum output frequency supported by the DS1075M-100?
The DS1075M-100 supports a maximum output frequency of 100.000 MHz, as specified in its part number suffix and confirmed in the Frequency Options table. This value represents the highest frequency achievable when the internal oscillator is selected and the programmable divider is bypassed (DIV1 = 1, N = 1). The device maintains ±0.5% initial tolerance and ±1% variation over temperature and voltage at this frequency.
Can the DS1075M-100 operate with an external crystal, and what is the maximum crystal frequency?
Yes, the DS1075M-100 supports crystal reference operation using a crystal connected between XTAL and OSCIN pins. The maximum crystal frequency is 25 MHz, as stated in the AC Electrical Characteristics table under "Maximum Input Frequency" for crystal reference. Operation above this frequency risks instability or failure to start; no external load capacitors are required due to integrated oscillator circuitry.
How does the synchronous output enable (OE) function prevent pulse truncation in the DS1075M-100?
The DS1075M-100 implements an "enabling sequencer" that samples OE with the prescaler output (MCLK) and gates the final output accordingly. When OE goes low while OUT is high, the device waits until the next high-to-low transition to disable OUT - ensuring no partial pulse is generated. This behavior preserves duty cycle integrity and avoids timing hazards in downstream logic, unlike asynchronous enable schemes.
What is the power consumption of the DS1075M-100 in power-down mode?
In power-down mode (activated by pulling PDN/SELX low when PDN bit = 1), the DS1075M-100 draws only 0.8 µA, as specified in the DC Electrical Characteristics table. This ultra-low current results from complete shutdown of the internal oscillator, OSCIN buffer, and output drivers - significantly lower than standby current during OE assertion alone, making it suitable for battery-backed or energy-harvesting systems.
Is the DS1075M-100 pin-compatible with other devices in the DS1075 family?
Yes, the DS1075M-100 shares identical pinout and package dimensions (300-mil DIP) with all DS1075M-x variants (e.g., DS1075M-80, DS1075M-66). Electrical characteristics such as supply current and jitter scale with output frequency, but pin functions, register structure, programming protocol, and timing behavior remain fully consistent across the family - enabling drop-in replacement for different frequency grades.
DS1075M-100 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc./Maxim Integrated
- Series:
- EconOscillator™
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- Oscillator, Fixed Frequency (Dual)
- Count:
- -
- Frequency:
- 100MHz
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Supply:
- 35 mA
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 8-PDIP
- Mounting Type:
- Through Hole
- Grade:
- -
- Qualification:
- -
DS1075M-100 FAQ
1.How can I place an order for DS1075M-100 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS1075M-100 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS1075M-100 reliable?
The price and inventory of DS1075M-100 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS1075M-100 is usually 5 days.
3.What payment methods are accepted for DS1075M-100?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS1075M-100 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS1075M-100?
DS1075M-100 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS1075M-100 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS1075M-100?
For technical support, including DS1075M-100 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS1075M-100 requirements.
6.How does Aetrix verify that DS1075M-100 is sourced from the original manufacturer or authorized distributors?
All DS1075M-100 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS1075M-100 meets industry standards.
7.What is the process for return or replacement of DS1075M-100?
All DS1075M-100 units undergo pre-shipment inspection (PSI). If there is an issue with DS1075M-100, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS1075M-100 part is unused and in its original packaging.
Return procedure for DS1075M-100:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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