Texas Instruments DS110DF111SQE/NOPB

Overview

DS110DF111SQE/NOPB from Texas Instruments is a dual-channel, low-power, multirate retimer IC for high-speed serial links. It performs independent CTLE equalization, clock and data recovery (CDR), and programmable transmit de-emphasis on each channel across 8.5–11.3 Gbps. Designed for SFF-8431-compliant front-port optical interconnects, it delivers <1×10⁻¹⁵ BER with adaptive 5-tap DFE and supports 25 MHz reference clock input.

For engineers reviewing the DS110DF111SQE/NOPB datasheet, DS110DF111SQE/NOPB pinout, DS110DF111SQE/NOPB application, or DS110DF111SQE/NOPB equivalent, key selection considerations include per-channel CDR lock time (10–30 ms), output VOD range (600–1300 mV_p-p), de-emphasis programmability (0 to –12 dB), adaptive CTLE up to 34 dB at 5.65 GHz, and WQFN-24 package compatibility with 4.0 mm × 4.0 mm PCB footprint.

Technical Context

The DS110DF111SQE/NOPB implements two fully independent data paths, each integrating a Continuous-Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), phase-locked loop (PLL) with 5 MHz bandwidth, and programmable CML output driver. Its dual-loop architecture enables simultaneous operation at subrates (½, ¼, ⅛ data rate) for legacy protocol support.

Each channel features autonomous CTLE adaptation triggered on signal detection or CDR reset, using internal Eye Opening Monitor (EOM) feedback. The device accepts AC-coupled CML inputs (100 Ω on-chip termination) and outputs, requires external 25 MHz ±100 ppm LVCMOS reference clock, and operates from single 3.3 V or 2.5 V supply with integrated regulator control via VIN/VDD pins.

Key Specifications

Pinout & Package

DS110DF111SQE/NOPB is housed in a 4.0 mm × 4.0 mm, 0.5 mm pitch, 24-pin WQFN (RTW) package with exposed thermal pad (DAP) requiring ≥4 vias to ground plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar retimer applications.

Compared with DS125DF111SQE/NOPB and DS100DF410RHAT, DS110DF111SQE/NOPB offers optimal cost-performance balance for dual-lane 10G optical interconnects, with guaranteed 8.5 Gbps operation, smallest footprint (4 mm × 4 mm), and lowest power (200 mW/channel), making it ideal for space-constrained SFP+ modules.

Availability

DS110DF111SQE/NOPB is available at Aetrix Electronics and suitable for front-port optical interconnects, SFF-8431 transceivers, and 10G/1G Ethernet backplanes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for DS110DF111SQE/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-speed interface solutions, with decades of expertise in signal integrity and serial connectivity ICs.

The DS110DF111SQE/NOPB belongs to TI's DS1xxDF retimer family, engineered specifically for multirate, low-power reconditioning of high-speed serial data in optical modules, telecom infrastructure, and enterprise networking equipment.

FAQ

What data rates does the DS110DF111SQE/NOPB support?

The DS110DF111SQE/NOPB supports full-rate operation from 8.5 to 11.3 Gbps per channel, plus subrates at ½, ¼, and ⅛ of those rates (e.g., 1.25 Gbps, 2.5 Gbps, 5.15625 Gbps). This enables interoperability with legacy 1G/10G Ethernet, CPRI, and SFF-8431-compliant optical modules. The DS110DF111SQE/NOPB achieves BER <1×10⁻¹⁵ across this entire range using adaptive CTLE and DFE.

Does the DS110DF111SQE/NOPB require an external crystal?

Yes, the DS110DF111SQE/NOPB requires an external 25 MHz ±100 ppm LVCMOS oscillator connected to the REFCLK_IN pin. It does not include an integrated crystal driver or oscillator circuit. The DS110DF111SQE/NOPB uses this reference to calibrate its internal VCO and achieve fast CDR lock (10–30 ms); the oscillator's voltage level must match the selected VIN supply (2.5 V or 3.3 V).

How is CTLE adaptation triggered on the DS110DF111SQE/NOPB?

CTLE adaptation on the DS110DF111SQE/NOPB initiates automatically upon first signal detection at the input or after a CDR reset event. It uses real-time feedback from the internal Eye Opening Monitor (EOM) to adjust CTLE gain settings and optimize horizontal/vertical eye opening. The DS110DF111SQE/NOPB completes adaptation within milliseconds and supports both SMBus-controlled and pin-strapped modes - though pin mode limits high-loss channel adaptation without register override.

Can the DS110DF111SQE/NOPB operate from a 3.3-V supply?

Yes, the DS110DF111SQE/NOPB supports dual-supply operation: 3.3 V ±10% on VIN and regulated 2.5 V ±5% on VDD (generated internally), or direct 2.5 V ±5% on both VIN and VDD. In 3.3 V mode, the DS110DF111SQE/NOPB draws ≤300 mA total supply current at 11.3 Gbps with DFE enabled, and all I/Os remain 3.3 V LVCMOS tolerant, including SCL/SDA and control pins.

What is the purpose of the LPF_CP_A and LPF_REF_A pins on the DS110DF111SQE/NOPB?

The LPF_CP_A and LPF_REF_A pins on the DS110DF111SQE/NOPB form the loop filter network for Channel A's PLL. A 22 nF capacitor must be placed between them to stabilize the phase-locked loop, directly impacting jitter transfer function and total jitter performance. Identical 22 nF filtering is required on LPF_CP_B/LPF_REF_B for Channel B. Incorrect capacitor value or placement degrades jitter suppression below the specified ≤7.5 ps (1E–12).