Texas Instruments DS110DF111SQ/NOPB

Overview

DS110DF111SQ/NOPB from Texas Instruments is a dual-channel, low-power, multirate retimer IC for high-speed serial links operating from 8.5 to 11.3 Gbps per channel. It integrates adaptive CTLE (up to 34 dB boost at 5.65 GHz), self-tuning 5-tap DFE, CDR, and programmable transmit drivers - enabling BER < 1×10⁻¹⁵ in lossy copper interconnects and optical front-ports. It is used in SFF-8431-compliant 10G Ethernet and CPRI interfaces.

For engineers reviewing the DS110DF111SQ/NOPB datasheet, DS110DF111SQ/NOPB pinout, DS110DF111SQ/NOPB application, or DS110DF111SQ/NOPB equivalent, key selection criteria include its 24-pin WQFN package, dual independent CDR lock capability, SMBus/EEPROM/pin-based configuration flexibility, and support for subrate locking (½, ¼, ⅛ data rates) for legacy compatibility.

Technical Context

The DS110DF111SQ/NOPB implements two fully independent data paths, each with a Continuous-Time Linear Equalizer (CTLE), clock-and-data recovery (CDR) using a VCO-based PLL with 5 MHz –3 dB bandwidth, and a programmable CML output driver. Its adaptive CTLE and DFE jointly compensate for channel loss up to ~34 dB at 5.65 GHz and mitigate ISI from long backplanes or multi-connector traces.

Each channel supports raw equalized data loopback, PRBS9/PRBS31 generation, and on-chip eye monitoring (HEO/VEO). The device requires a 25 MHz ±100 ppm LVCMOS reference clock (REFCLK_IN) and operates from a single 3.3-V or 2.5-V supply, delivering 200 mW/channel typical power consumption at 11.3 Gbps with DFE enabled.

Key Specifications

Pinout & Package

The DS110DF111SQ/NOPB is housed in a 4.0 mm × 4.0 mm, 24-pin WQFN (RTW) package with 0.5 mm pitch and exposed thermal pad (DAP) requiring ≥4 vias to ground for thermal and EMI performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar retimer applications.

Compared with DS125DF111 and DS100DF410, the DS110DF111SQ/NOPB uniquely balances 8.5–11.3 Gbps coverage, integrated DFE, and pin compatibility within TI's retimer family - making it optimal for SFP+/XFP modules and CPRI front-haul where subrate lock and low-power operation are mandatory.

Availability

DS110DF111SQ/NOPB is available at Aetrix Electronics and suitable for 10G Ethernet front-ports, SFF-8431 optical transceivers, CPRI baseband units, and high-density switch fabric interconnects requiring stable component supply across extended product lifecycles.

Supply support for DS110DF111SQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-speed interface solutions for industrial, communications, and automotive markets.

The DS110DF111SQ/NOPB belongs to TI's high-speed retimer product line, designed specifically to extend reach and improve signal integrity in multigigabit serial links using adaptive equalization and jitter cleanup - targeting optical module, networking, and wireless infrastructure applications.

FAQ

What data rates does the DS110DF111SQ/NOPB support, and how does subrate locking work?

The DS110DF111SQ/NOPB supports full-rate operation from 8.5 to 11.3 Gbps per channel and locks to integer subrates - specifically ½, ¼, and ⅛ of any supported full rate (e.g., 5.15625 Gbps, 2.578125 Gbps, or 1.2890625 Gbps). Subrate locking uses internal digital dividers and VCO pre-scaling to maintain phase alignment while reducing bandwidth requirements; it is essential for interoperability with legacy 1G/2.5G/5G Ethernet PHYs and CPRI baseband units. This capability is implemented in hardware and requires no firmware intervention.

Does the DS110DF111SQ/NOPB require an external crystal or oscillator?

No, the DS110DF111SQ/NOPB does not include a crystal oscillator driver and requires an external 25 MHz ±100 ppm LVCMOS clock source connected to REFCLK_IN. The reference clock is used for VCO calibration and lock detection but does not directly generate the recovered clock - that is derived entirely from the input data stream via the CDR PLL. A standard commercial 25 MHz oscillator (not a crystal) satisfies this requirement, and its voltage level must match the selected supply mode (2.5 V or 3.3 V).

How does the DS110DF111SQ/NOPB handle input signal detection and loss-of-signal indication?

The DS110DF111SQ/NOPB detects valid input signals at levels ≥15 mV_p-p (SDL threshold) and asserts LOS/INT# low when signal falls below that level. The default behavior is loss-of-signal indication, but LOS/INT# can be reconfigured via register 0x1C to function as a general-purpose interrupt triggered when the Eye Opening Monitor (EOM) reports HEO or VEO below user-defined thresholds. Signal detect is performed independently per channel and is active before CDR lock acquisition.

Can the DS110DF111SQ/NOPB operate with only pin-strapping, or is SMBus required?

The DS110DF111SQ/NOPB supports three configuration modes: SMBus register access, external EEPROM boot, and 4-level pin strapping (with ENSMB = LOW). Pin strapping enables basic operation at 1.25 Gbps and 10.3125 Gbps with limited VOD and de-emphasis control - sufficient for simple fixed-rate applications. However, full functionality - including adaptive CTLE/DFE, subrate locking, EOM readback, and fine-grained transmit settings - requires SMBus or EEPROM configuration. Pin mode is intended for prototyping or cost-sensitive deployments where flexibility is secondary.

What thermal design considerations apply to the DS110DF111SQ/NOPB in a 4.0 mm × 4.0 mm WQFN package?

The DS110DF111SQ/NOPB has a junction-to-board thermal resistance (RθJB) of 13.4 °C/W and requires the exposed thermal pad (DAP) to be soldered to a solid ground plane using ≥4 thermal vias. In a 2-layer board with 1 oz copper, ambient temperatures up to +85°C, and 200 mW/channel dissipation, the junction temperature remains within spec if the PCB maintains ≥2 in² of continuous copper under the DAP. TI recommends avoiding thermal reliefs on DAP connections and verifying temperature rise with IR imaging during system validation.